Semiconductor device and information processing system including the same
View Patent ↗A semiconductor device includes a plurality of core chips and an interface chip that controls the core chips. Each of the core chips and the interface chip includes plural through silicon vias that penetrate a semiconductor substrate and plural pads respectively connected to the through silicon vias. The through silicon vias include a through silicon via of a power source system to which a power source potential or a ground potential is supplied, and a through silicon via of a signal system to which various signals are supplied. Among the pads, at least an size of a pad connected to the through silicon via of the power source system is larger than a size of a pad connected to the through silicon via of the signal system. Therefore, a larger parasitic capacitance can be secured.
1. A semiconductor device comprising:
a semiconductor substrate;
first and second penetration electrodes that penetrate the semiconductor substrate;
first and second wiring pads respectively connected to the first and second penetration electrodes, wherein the first penetration electrode is supplied with a signal, the second penetration electrode is supplied with a power source potential, and the second wiring pad has larger size than the first wiring pad; and
a signal wiring, wherein a plurality of the second wiring pads are provided on different wiring layers from each other, the signal wiring is provided on a same wiring layer as one of the second wiring pads, and at least a part of the signal wiring is overlapped with other one of the second wiring pads in a planar view.
2. A semiconductor device comprising:
a semiconductor substrate;
first and second bumps provided over the semiconductor substrate;
first and second penetration electrodes each penetrating the semiconductor substrate;
a first conductive structure making a first electrical path between the first bump and the first penetration electrode; and
a second conductive structure making a second electrical path between the second bump and the second penetration electrode;
the second conductive structure being smaller in resistance value than the first conductive structure.
3. The semiconductor device as claimed in claim 2 , wherein the first and second bumps are substantially the same in size as each other.
4. The semiconductor device as claimed in claim 3 , wherein the first and second penetration electrodes are the same in size as each other.
5. The semiconductor device as claimed in claim 2 , wherein the first conductive structure further includes a plurality of first pads stacked with one another such that vertically adjacent two of the first pads are connected via at least one first through electrode and the second conductive structure further includes a plurality of second pads stacked with one another such that vertically adjacent two of the second pads are connected via at least one second through electrode and at least one of the second pads is larger in size than at least one of the first pads.
6. The semiconductor device as claimed in claim 2 , further comprising a plurality of transistors provided on the semiconductor substrate.
7. The semiconductor device as claimed in claim 2 , further comprising first and second insulating rings each surrounding an associated one of the first and second penetration electrodes to electrically separate the first penetration electrode from the second penetration electrode.
8. The semiconductor device as claimed in claim 2 , wherein the first and second penetration electrodes includes top surfaces coupled to the first and second conductive structures, respectively, and bottom surfaces, the semiconductor device further comprises a third bump provided on the bottom surface of the first penetration electrode and a fourth bump provided on the bottom surface of the second penetration electrode.
9. The semiconductor device as claimed in claim 8 , wherein the third and fourth bumps are substantially the same in size as each other.
10. A semiconductor device comprising:
a semiconductor substrate;
first and second penetration electrodes each penetrating the semiconductor substrate:
a multi-level wiring structure formed on the semiconductor substrate, the multi-level wiring structure comprising a lower-level wiring, an upper-level wiring and an interlayer insulating film between the lower-level wiring and the upper-level wiring;
a first wiring pad formed as the lower-level wiring and electrically connected to the first penetration electrode;
a second wiring pad formed as the upper-level wiring;
a plurality of first through electrodes each formed in the interlayer insulating film to form an electrical connection between the first and second wiring pads;
a third wiring pad formed as the lower-level wiring and electrically connected to the second penetration electrode;
a fourth wiring pad formed as the upper-level wiring; and
a plurality of second through electrodes each formed in the interlayer insulating film to form an electrical connection between the third and fourth wiring pads,
wherein the first wiring pad is greater in size than the third wiring pad.
11. The semiconductor device as claimed in claim 10 , wherein the first through electrodes are greater in number than the second through electrodes.
12. The semiconductor device as claimed in claim 10 , wherein the first wiring pad is greater in size than the second wiring pad.
13. The semiconductor device as claimed in claim 10 , further comprising:
first and second insulation rings each penetrating the semiconductor substrate to surround an associated one of the first and second penetration electrodes.
14. The Semiconductor device as claimed in claim 13 , wherein the semiconductor substrate includes an active region between the first and second insulation rings, and the semiconductor device further comprises at least one transistor formed in the active region of the semiconductor substrate.
15. The semiconductor device as claimed in claim 10 , wherein the first and second penetration electrodes are substantially the same in size as each other.
16. The semiconductor device as claimed in claim 10 , wherein the first penetration electrode is configured to be supplied with a power source voltage and the second penetration electrode is configured to be supplied with a signal.
17. The semiconductor device as claimed in claim 10 , wherein the first and second penetration electrodes are coupled to the first and second wiring pads at top surfaces thereof, respectively, and
wherein the semiconductor device further comprises:
a first bump connected to a bottom surface of the first penetration electrode; and
a second bump connected to a bottom surface of the second penetration electrode, the second bump being substantially the same in size as the first bump.
18. A semiconductor device comprising:
a semiconductor substrate;
first and second penetration electrodes each penetrating the semiconductor substrate; and
first and second wiring pads respectively connected to the first and second penetration electrodes,
wherein the first and second penetration electrodes are substantially the same in size as each other and the first and second wiring pads are different in size from each other.
19. The semiconductor device as claimed in claim 18 , wherein the first and second penetration electrodes are coupled to the first and second wiring pads at top surfaces thereof, respectively, and
wherein the semiconductor device further comprises:
a first bump connected to a bottom surface of the first penetration electrode; and
a second bump connected to a bottom surface of the second penetration electrode, the second bump being substantially the same in size as the first bump.
20. The semiconductor device as claimed in claim 18 , further comprising:
first and second insulation rings each penetrating the semiconductor substrate to surround an associated one of the first and second penetration electrodes.
21. The semiconductor device as claimed in claim 20 , wherein the semiconductor substrate includes an active region between the first and second insulation rings, and the semiconductor device further comprises at least one transistor formed in the active region of the semiconductor substrate.
22. The semiconductor device as claimed in claim 18 , wherein the first penetration electrode is configured to be supplied with a power source voltage and the second penetration electrode is configured to be supplied with a signal.