Max-log-map equivalence log likelihood ratio generation soft viterbi architecture system and method
A modified soft output Viterbi algorithm (SOVA) detector receives a sequence of soft information values and determines a best path and an alternate path for each soft information value and further determines, when the best and alternate paths lead to the same value for a given soft information value, whether there is a third path departing from the alternate path that leads to an opposite decision with respect to the best path for a given soft information value. The SOVA detector then considers this third path when updating the reliability of the best path. The modified SOVA detector achieves max-log-map equivalence effectively through the Fossorier approach and includes modified reliability metric units for the first N stages of the SOVA detector, where N is the memory depth of a given path, and includes conventional reliability metric units for the remaining stages of the detector.
1. A Viterbi detector, comprising:
an input terminal configured to receive a signal that represents a sequence of values;
a register; and
a recovery circuit coupled to the input terminal and to the register, the recovery circuit configured to recover only groups of values having a same parity and load the recovered groups into the register.
2. The Viterbi detector of claim 1 wherein the parity comprises odd parity.
3. The Viterbi detector of claim 1 wherein the groups of values each comprises a respective set of data bits and a respective set of code bits.
4. The Viterbi detector of claim 1 wherein the groups of values each comprises a respective set of data bits, a respective set of code bits, and a respective parity bit.
5. The Viterbi detector of claim 1 wherein the groups of values each comprise a respective code word that includes twenty six bits, one of the bits being a parity bit.
6. The Viterbi detector of claim 1 wherein the recovery circuit is configured to identify the respective beginnings of each of the groups of values.
7. The Viterbi detector of claim 1 wherein the sequence of values comprises a sequence of binary values.
8. The Viterbi detector of claim 1 wherein:
the register comprises a shift register; and
the recovery circuit is configured to shift the recovered groups into the shift register.
9. The Viterbi detector of claim 1 wherein:
the values in the groups comprise respective code words; and
the recovery circuit is configured to generate a recovered sequence of code words.
10. The Viterbi detector of claim 1 wherein the recovery circuit is configured to generate the recovered groups of values by:
calculating a set of path lengths from a first and second sets of branch lengths;
identifying a state path that corresponds to the smallest one of the path lengths; and
generating the recovered groups of values equal to the sequence of states in the state path.
11. A system, comprising:
a Viterbi detector, including:
an input terminal configured to receive a signal that represents a sequence of values;
a register; and
a recovery circuit coupled to the input terminal and to the register, the recovery circuit configured to recover only groups of values having a same parity, and load the recovered groups into the register.
12. The system of claim 11 wherein the system comprises a disk-drive system.
13. The system of claim 11 further comprising:
a data-storage disk having a surface and configured to store information values; and
a motor coupled to and configured to rotate the disk.
14. The system of claim 11 further comprising:
a read head configured to generate a read signal; and
a read-head positioning assembly configured to move the read head over the surface of the disk.
15. An integrated circuit, comprising:
a Viterbi detector, including:
an input terminal configured to receive a signal that represents a sequence of values;
a register; and
a recovery circuit coupled to the input terminal and to the register, the recovery circuit configured to recover only groups of values having a same parity, and load the recovered groups into the register.
16. The integrated circuit of claim 15 further comprising a single integrated circuit die.
17. The integrated circuit of claim 15 further comprising multiple integrated circuit dies.
18. The integrated circuit of claim 15 further comprising a processor.