Statistical delay and noise calculation considering cell and interconnect variations
The electrical circuit timing method provides accurate nominal delay together with the delay sensitivities with respect to different circuit elements (e.g., cells, interconnects, etc.) and variational parameters (e.g., process variations; environmental variations). All the sensitivity computations are based on closed-form formulas; as a consequence, the method provides rapidly and at low cost high accuracy and high numerical stability.
1. A computer-implemented method for calculating crosstalk delay of an integrated circuit the method comprising:
receiving information describing one or more aggressor cells comprising an aggressor cell output pin and at least one or more aggressor cell input pins, and one or more victim cells comprising a victim cell output pin and at least one or more victim cell input pins;
determining, by a computer, an overall non-crosstalk voltage variation, the overall non-crosstalk voltage variation comprising a first output voltage waveform of a victim logic cell as a function of one or more process variation parameters when no aggressor cells are present;
determining, by the computer, an overall crosstalk noise voltage variation, the overall crosstalk noise voltage variation comprising a second output voltage waveform of the victim logic cell as a function of one or more process variation parameters when at least one or more aggressor cells are present;
determining a rate of change of the overall non-crosstalk voltage variation;
determining a rate of change of the overall crosstalk noise voltage variation; and
determining, by the computer, at least one or more crosstalk delay sensitivities by calculating a ratio between the sum of the overall non-crosstalk voltage variation and the overall crosstalk noise voltage variation, and the sum of the rate of change of the overall non-crosstalk voltage variation and the rate of change of the overall crosstalk noise voltage variation.
2. The computer-implemented method of claim 1 further comprising:
calculating the crosstalk delay as a weighted sum of each of the one or more crosstalk delay sensitivities.
3. The method of claim 1 , wherein determining the overall non-crosstalk voltage variation comprises:
calculating a non-crosstalk output waveform for every input pin of the victim logic cell.
4. The method of claim 3 , wherein determining the overall non-crosstalk voltage variation further comprises:
calculating a statistical max from the non-crosstalk output waveform of every input pin.
5. The method of claim 1 , wherein determining the overall non-crosstalk voltage variation comprises:
calculating the overall non-crosstalk voltage variation using a two pole approximation.
6. The method of claim 1 , wherein determining the overall crosstalk noise voltage variation comprises:
calculating a crosstalk noise envelope for every aggressor cell input pin of every aggressor cell; and
calculating a crosstalk noise envelope statistical max for every aggressor cell, the crosstalk noise envelope statistical max comprising a largest crosstalk noise envelope between the crosstalk noise envelope of every aggressor cell input pin of one aggressor cell.
7. The method of claim 6 , wherein determining the overall crosstalk noise voltage variation further comprises:
calculating a statistical sum of the crosstalk noise envelope statistical max of every aggressor cell.
8. A non-transitory computer readable medium configured to store instructions, the instructions when executed by a processor cause the processor to:
receive information describing one or more aggressor cells comprising an aggressor cell output pin and at least one or more aggressor cell input pins, and one or more victim cells comprising a victim cell output pin and at least one or more victim cell input pins;
determine an overall non-crosstalk voltage variation, the overall non-crosstalk voltage variation comprising a first output voltage waveform of a victim logic cell as a function of one or more process variation parameters when no aggressor cells are present;
determine an overall crosstalk noise voltage variation, the overall crosstalk noise voltage variation comprising a second output voltage waveform of the victim logic cell as a function of one or more process variation parameters when at least one or more aggressor cells are present;
determine a rate of change of the overall non-crosstalk voltage variation;
determine a rate of change of the overall crosstalk noise voltage variation; and
determine at least one or more crosstalk delay sensitivities by calculating a ratio between the sum of the overall non-crosstalk voltage variation and the overall crosstalk noise voltage variation, and the sum of the rate of change of the overall non-crosstalk voltage variation and the rate of change of the overall crosstalk noise voltage variation.
9. The non-transitory computer readable medium of claim 8 further comprising instructions that cause the processor to:
calculate the crosstalk delay as a weighted sum of each of the one or more crosstalk delay sensitivities.
10. The non-transitory computer readable medium of claim 8 , wherein determining the overall non-crosstalk voltage variation causes the processor to:
calculate a non-crosstalk output waveform for every input pin of the victim logic cell.
11. The non-transitory computer readable medium of claim 10 , wherein determining the overall non-crosstalk voltage variation causes the processor to:
calculate a statistical max from the non-crosstalk output waveform of every input pin.
12. The non-transitory computer readable medium of claim 8 , wherein determining the overall non-crosstalk voltage variation causes the processor to:
calculate the overall non-crosstalk voltage variation using a two pole approximation.
13. The non-transitory computer readable medium of claim 8 , wherein determining the overall crosstalk noise voltage variation causes the processor to:
calculate a crosstalk noise envelope for every aggressor cell input pin of every aggressor cell; and
calculate a crosstalk noise envelope statistical max for every aggressor cell, the crosstalk noise envelope statistical max comprising a largest crosstalk noise envelope between the crosstalk noise envelope of every aggressor cell input pin of one aggressor cell.
14. The non-transitory computer readable medium of claim 13 , wherein determining the overall crosstalk noise voltage variation causes the processor to:
calculate a statistical sum of the crosstalk noise envelope statistical max of every aggressor cell.
15. A system for calculating crosstalk delay of an integrated circuit comprising:
a computer processor; and
a computer-readable storage medium storing computer program modules configured to execute on the computer processor, the computer program modules configured to:
receive information describing one or more aggressor cells comprising an aggressor cell output pin and at least one or more aggressor cell input pins, and one or more victim cells comprising a victim cell output pin and at least one or more victim cell input pins;
determine an overall non-crosstalk voltage variation, the overall non-crosstalk voltage variation comprising a first output voltage waveform of a victim logic cell as a function of one or more process variation parameters when no aggressor cells are present;
determine an overall crosstalk noise voltage variation, the overall crosstalk noise voltage variation comprising a second output voltage waveform of the victim logic cell as a function of one or more process variation parameters when at least one or more aggressor cells are present;
determine a rate of change of the overall non-crosstalk voltage variation;
determine a rate of change of the overall crosstalk noise voltage variation; and
determine at least one or more crosstalk delay sensitivities by calculating a ratio between the sum of the overall non-crosstalk voltage variation and the overall crosstalk noise voltage variation, and the sum of the rate of change of the overall non-crosstalk voltage variation and the rate of change of the overall crosstalk noise voltage variation.
16. The system of claim 15 wherein the computer program modules are further configured to:
calculate the crosstalk delay as a weighted sum of each of the one or more crosstalk delay sensitivities.
17. The system of claim 15 , wherein determining the overall non-crosstalk voltage variation causes the computer program modules to:
calculate a non-crosstalk output waveform for every input pin of the victim logic cell.
18. The system of claim 17 , wherein determining the overall non-crosstalk voltage variation causes the computer program modules to:
calculate a statistical max from the non-crosstalk output waveform of every input pin.
19. The system of claim 15 , wherein determining the overall non-crosstalk voltage variation causes the computer program modules to:
calculate the overall non-crosstalk voltage variation using a two pole approximation.
20. The system of claim 15 , wherein determining the overall crosstalk noise voltage variation causes the computer program modules to:
calculate a crosstalk noise envelope for every aggressor cell input pin of every aggressor cell; and
calculate a crosstalk noise envelope statistical max for every aggressor cell, the crosstalk noise envelope statistical max comprising a largest crosstalk noise envelope between the crosstalk noise envelope of every aggressor cell input pin of one aggressor cell.
21. The system of claim 20 , wherein determining the overall crosstalk noise voltage variation causes the computer program modules to:
calculate a statistical sum of the crosstalk noise envelope statistical max of every aggressor cell.