Fractal interconnects for neuro-electronic interfaces and implants using same
View Patent ↗A neuro-electronic interface device has a micro-electrode electrically connected to an interconnect that has scaling gradients between 1.1 and 1.9 over a scaling range of at least one order of magnitude. The device preferably has an array of such fractal interconnects in electrical contact with an array of micro-electrodes. Such fractal interconnect arrays may be components of implants including a retinal implant device having an array of photodetectors in electrical contact with the array of micro-electrodes. The interconnects may be fabricated by forming nanoscale particles and depositing them onto a non-conductive surface that is smooth except for electrodes which serve as nucleation sites for the formation of fractal interconnect structures through diffusion limited aggregation.
1. A neuro-electronic interface device comprising:
a micro-electrode;
an interconnect in electrical contact with the micro-electrode;
wherein the interconnect is conductive and is fabricated on a non-conductive surface;
wherein the interconnect is a dendrite having scaling gradients that vary between 1.1 and 1.9 over a scaling range of more than one order of magnitude of magnification.
2. The device of claim 1 wherein the interconnect has a fractal dimension D equal to a value between 1.4 and 1.9 over a scaling range of at least one order of magnitude below 200 μm.
3. The device of claim 1 further comprising:
an array of micro-electrodes; and
an array of interconnects in electrical contact with the array of micro-electrodes;
wherein the interconnects are in one-to-one correspondence with the micro-electrodes.
4. The device of claim 1 :
wherein the non-conductive surface is a non-conductive planar layer fabricated on a substrate;
wherein the micro-electrode is fabricated on the substrate;
wherein a surface roughness of the planar layer is less than a surface roughness of the substrate.
5. The device of claim 4 wherein the planar layer has a mean roughness (Rms) less than 1 nm.
6. The device of claim 5 wherein the planar layer is atomically flat.
7. The device of claim 1 wherein the interconnect has a fractal dimension between 1.6 and 1.9 over a scaling range of at least two orders of magnitude below 200 μm.