3D semiconductor device
View Patent ↗A wafer includes a group of tiles of programmable logic formed thereon, wherein each tile comprises a micro control unit (MCU) communicating with adjacent MCUs, and wherein each MCU is controlled in a predetermined order of priority by adjacent MCUs; and dice lines on the wafer to separate the group into one or more end-devices.
1. A wafer, comprising:
a group of tiles of programmable logic formed thereon, wherein each tile comprises a micro control unit (MCU) communicating with adjacent MCUs on one layer to configure the group of tiles, and wherein each MCU is controlled in a predetermined order of priority by adjacent MCUs, where each MCU comprises a processor and memory, and where the MCUs control and initialize the programmable logic; and
dice lines on the wafer to separate the group into a plurality end-devices.
2. The wafer of claim 1 , wherein the dice lines separate the wafer into various die sizes.
3. The wafer of claim 1 , comprising one or more dies coupled to the tiles using Through Silicon Vias.
4. The wafer of claim 1 , wherein the dies are logic dies, comprising dedicated masks coupled to unused dice lines to connect individual tiles according to a desired die size.
5. The wafer of claim 1 , wherein the programmable logic comprises field programmable gate array (FPGA).
6. The wafer of claim 1 , wherein the programmable logic comprises field programmable gate array (FPGA) and wherein the MCU loads the FPGA with programmed function and initialize the FPGA.
7. The wafer of claim 1 , wherein an adjacent MCU is controlled by a west MCU if one exists, and if not, by a south MCU.
8. The wafer of claim 1 , wherein the control inputs to one MCU are used to control the end-device and spread to other tiles.
9. The wafer of claim 1 , wherein the MCUs are utilized for user functions during end-device operation after the end-device has completed set up or initialization.
10. The wafer of claim 1 , comprise Input/Output (I/O) circuit connected to it by Through Silicon Via (TSV).
11. A semiconductor device, comprising;
a first mono-crystallized semiconductor layer; and
a second mono-crystallized semiconductor layer;
wherein said first and second mono-crystallized semiconductor layers are overlaying one on top of the other, and
wherein said second mono-crystallized semiconductor layer comprise repeating memory structure with sub structures defined by etching as a customization step after the repeating memory structure had been fabricated.
12. The device according to claim 11 , wherein said second mono-crystallized semiconductor layer comprises logic circuits, wherein said logic circuit communicates with an external device through I/O circuits constructed on a third mono-crystallized semiconductor layer.
13. The device according to claim 11 comprising a third mono-crystallized semiconductor layer, wherein said third mono-crystallized semiconductor layer comprise I/O circuits.
14. The device according to claim 12 , wherein said I/O circuits comprise Through Silicon Via (TSV).
15. The device according to claim 11 , wherein said second mono-crystallized semiconductor layer comprises programmable logic circuits.
16. The device according to claim 11 , wherein said second mono-crystallized semiconductor layer comprises gate-array.
17. The device according to claim 13 , comprising processing a memory structure on a different line than said I/O circuits.
18. The device according to claim 11 , wherein said device is used in a mobile system.
19. The device according to claim 11 , comprising one or more masks used to construct said device are used to fabricate another device.
20. The device according to claim 11 , wherein the layer is etched to form dice lines.