IP Library Granted Patent US 8,008,681
Granted Patent B2
US 8,008,681 · App. 12/941,627 · Granted Aug 30, 2011

Diode having vertical structure and method of manufacturing the same

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Quick Facts
Patent No.
US 8,008,681
App. No.
12/941,627
Granted
Aug 30, 2011
Kind
B2
Abstract

A light emitting diode includes a conductive layer, an n-GaN layer on the conductive layer, an active layer on the n-GaN layer, a p-GaN layer on the active layer, and a p-electrode on the p-GaN layer. The conductive layer is an n-electrode.

Claims (47)

1. A light emitting device comprising:

a first metal layer comprising Au;

a first electrode on the first metal layer, the first electrode serving as a reflective layer;

a GaN-based semiconductor structure having a first surface on the first electrode, the semiconductor structure comprising a first-type layer, an active layer on the first-type layer, and a second-type layer on the active layer;

a second electrode on a second surface of the semiconductor structure, wherein the second surface is opposite the first surface; and

a second metal layer comprising Au on the second electrode,

wherein the first electrode and the second surface are configured such that the first electrode reflects light from the active layer back through the second surface, and wherein the first electrode and the second electrode are arranged on the opposite surfaces of the semiconductor structure, respectively, whereby enhancing brightness of the device.

2. The device according to claim 1 , wherein the first electrode comprises at least one of Al, Ti, Cr, and Au.

3. The device according to claim 1 , wherein the second electrode comprises at least one of Ni, Au, Pd, and Pt.

4. The device according to claim 1 , wherein the active layer comprises AlInGaN.

5. The device according to claim 1 , wherein the active layer comprises at least one of a quantum well layer and a double hetero structure.

6. The device according to claim 1 , wherein the active layer has about 22% of indium composition.

7. The device according to claim 1 , wherein the active layer has about 40% of indium composition.

8. The device according to claim 1 , wherein the active layer has 22% to 40% of indium composition.

9. The device according to claim 1 , further comprising a cladding layer on the active layer.

10. The device according to claim 9 , wherein the cladding layer is arranged between the active layer and the second-type layer.

11. The device according to claim 9 , wherein the cladding layer comprises AlGaN.

12. The device according to claim 9 , wherein the first metal layer is arranged at the bottom of the device.

13. The device according to claim 1 , wherein the first metal layer contacts the first electrode.

14. The device according to claim 1 , wherein the first metal layer is configured to serve as a first pad.

15. The device according to claim 1 , wherein the second metal layer is arranged at the top of the device.

16. The device according to claim 1 , wherein the second metal layer is configured to serve as a second pad.

17. The device according to claim 1 , wherein the second metal layer contacts the second electrode.

18. The device according to claim 1 , wherein the second metal layer overlaps the second electrode.

19. The device according to claim 1 , wherein a thickness of the second metal layer is about 0.5 μm or higher.

20. The device according to claim 1 , wherein the second electrode is arranged at or near an edge of the second surface.

21. The device according to claim 1 , further comprising a transparent layer on the semiconductor structure.

22. The device according to claim 21 , wherein the transparent layer comprises a transparent conductive layer.

23. The device according to claim 21 , the transparent layer comprises oxide.

24. The device according to claim 21 , wherein the transparent layer comprises indium-tin-oxide.

25. The device according to claim 1 , further comprising a buffer layer between the first-type layer and the first electrode.

26. The device according to claim 25 , wherein a thickness of the buffer layer is about 1-2 μm.

27. The device according to claim 1 , wherein the first metal layer and the second metal layer are arranged on the opposite surfaces of the semiconductor structure, respectively.

28. The device according to claim 1 , wherein the first-type is n-type and the second-type is p-type.

29. The device according to claim 1 , wherein the first-type layer is doped with Si.

30. The device according to claim 29 , wherein the doping concentration of Si is about 10 17 cm −3 or greater.

31. The device according to claim 1 , wherein the second-type layer is doped with Mg.

32. The device according to claim 31 , wherein the doping concentration of Mg is about 10 17 cm −3 or greater.

33. The device according to claim 1 , wherein the first electrode has a surface facing the first surface, and wherein the area of the first surface is substantially the same as the area of the surface of the first electrode.

34. The device according to claim 1 , wherein a width of the first electrode is substantially the same as a width of the first metal layer.

35. The device according to claim 1 , wherein a width of the second electrode is substantially the same as a width of the second metal layer.

36. The device according to claim 1 , wherein a width of the active layer is substantially the same as a width of the first-type layer.

37. The device according to claim 36 , wherein the width of the active layer is configured to enhance brightness of the device.

38. The device according to claim 1 , wherein a width of the active layer is substantially the same as a width of the device.

39. The device according to claim 1 , wherein the first electrode and the second electrode are substantially vertically arranged with respect to the semiconductor structure so as to reduce an effect from static electricity therebetween.

40. The device according to claim 1 , wherein the first electrode and the second electrode are substantially vertically arranged with respect to the semiconductor structure so as to be suitable for a high voltage device.

41. The device according to claim 1 , wherein the first electrode and the second electrode are substantially vertically arranged with respect to the semiconductor structure so as to enhance brightness of the device.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 25, 2021
From: LG INNOTEK CO., LTD.
To: SUZHOU LEKIN SEMICONDUCTOR CO., LTD.
Reel/Frame 056366/0335 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 15, 2013
From: LG ELECTRONICS, INC.
To: LG INNOTEK CO. LTD.
Reel/Frame 031410/0169 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 8, 2010
From: YOO, MYUNG CHEOL
To: LG ELECTRONICS INC.
Reel/Frame 025332/0081 →