Method for integrating SONOS non-volatile memory into a standard CMOS foundry process flow
An embodiment of a method is disclosed to integrate silicon oxide nitride oxide silicon (SONOS) non-volatile memory (NVM) into a conventional complementary metal oxide semiconductor (CMOS) semiconductor foundry process flow. An embodiment of the method only adds a few additional steps to a standard CMOS foundry process flow and makes minor changes to the rest of the baseline CMOS foundry process flow to form a new process module that includes both CMOS devices and an embedded SONOS NVM.
1. A method for integrating silicon oxide nitride oxide silicon (SONOS) non-volatile memory (NVM) into a standard complementary metal oxide semiconductor (CMOS) foundry process flow, comprising:
performing standard CMOS foundry process flow, including:
forming an alignment layer on a silicon substrate;
forming twin-wells on the silicon wafer to form a plurality of devices on the silicon substrate; and
isolating neighboring devices on the silicon substrate;
patterning a memory window implant layer on the silicon substrate using a memory window implant mask; and
patterning a stack removal photoresist layer using a stack removal photoresist mask, wherein the memory window implant mask is smaller than the stack removal photoresist mask.
2. The method of claim 1 , wherein the patterning the memory window implant layer step selectively sets a threshold voltage of a SONOS transistor.
3. The method of claim 1 , wherein the stack removal photoresist layer is defined by the stack removal photoresist mask to allow a SONOS stack to be selectively removed from all regions of a silicon wafer except SONOS memory cell regions.
4. The method of claim 3 , wherein the SONOS stack includes a tunnel oxide layer, an oxynitride layer, and a capping oxide layer.
5. The method of claim 1 , wherein the patterning the memory window implant layer step includes patterning the memory window implant layer using memory window implant photoresist, forming patterned SONOS memory cell regions.
6. The method of claim 5 , wherein the patterning the memory window implant layer step further includes performing ion implantation through a scatter oxide layer to set a threshold voltage of a SONOS transistor.
7. The method of claim 6 , wherein the patterning the memory window implant layer step further includes, with the memory window implant photoresist still on wafers, wet etching the wafers to remove the scatter oxide layer in a memory window opening defined by the memory window implant mask.
8. The method of claim 7 , wherein the patterning the memory window implant layer step further includes stripping the memory window implant photoresist and growing a tunnel oxide layer.
9. The method of claim 8 , wherein the patterning the memory window implant layer step further includes depositing an oxynitride layer.
10. The method of claim 9 , wherein the patterning the memory window implant layer step further includes oxidizing the oxynitride layer to form a capping oxide layer.
11. The method of claim 10 , wherein the patterning the stack removal photoresist layer step includes patterning the SONOS stack using the stack removal photoresist mask.
12. The method of claim 11 , wherein the patterning the stack removal photoresist layer step further includes dry etching the wafers to remove the capping oxide layer and the oxynitride layer from the wafers except over the patterned SONOS memory cell regions.
13. The method of claim 12 , wherein the patterning the stack removal photoresist layer step further includes, with the stack removal photoresist mask still on the wafers, removing the scatter oxide layer over CMOS gates using a wet etch.
14. The method of claim 13 , wherein the patterning the stack removal photoresist layer step further includes stripping the stack removal photoresist mask.
15. A method for forming silicon oxide nitride oxide silicon (SONOS) non-volatile memory (NVM) as part of a standard complementary metal oxide semiconductor (CMOS) foundry process flows, comprising:
patterning a memory window implant layer using memory window implant photoresist and a memory window implant mask, forming patterned SONOS memory cell regions;
growing a tunnel oxide layer;
depositing an oxynitride layer
forming a capping oxide layer;
patterning a stack removal photoresist layer defined by a stack removal photoresist mask, wherein the memory window implant mask is smaller than the stack removal photoresist mask.
16. The method of claim 15 , wherein the memory window implant layer is patterned to selectively set a threshold voltage of a SONOS transistor.
17. The method of claim 15 , wherein the stack removal photoresist layer allows a SONOS stack to be selectively removed from all regions of a silicon wafer except SONOS memory cell regions.
18. The method of claim 15 , wherein the patterning the memory window implant layer step includes performing ion implantation through a scatter oxide layer to set a threshold voltage of a SONOS transistor.
19. The method of claim 18 , wherein the patterning the memory window implant layer step further includes, with the memory window implant photoresist still on wafers, wet etching the wafers to remove the scatter oxide layer in a memory window opening defined by the memory window implant mask.
20. The method of claim 19 , wherein the patterning the stack removal photoresist layer step further includes:
dry etching the wafers to remove the capping oxide layer and the oxynitride layer from the wafers except over the patterned SONOS memory cell regions;
with the stack removal photoresist mask still on the wafers, removing the scatter oxide layer over CMOS gates using a wet etch; and
stripping the stack removal photoresist mask.