Wrapper cell for hierarchical system on chip testing
Wrapper cells for simultaneous testing of parent functional elements and child functional elements in a hierarchical SoC (System on Chip) provide a substantially reduced integrated circuit footprint by eliminating a multiplexer and providing simpler interconnections. Identical wrapper cells may be used for input and output data lines reducing the cost of the cell library.
1. In an integrated circuit having at least a first and second interconnected functional element on a substrate, the functional elements having data lines providing inputs and outputs, and a plurality of wrapper cells for integrated circuit testing placed in series with data lines of the first and second functional elements, the wrapper cells comprising:
a functional input receiving an output from the first functional element;
a functional output providing an input to the second functional element;
two test data inputs each for receiving test data;
two test data outputs each for outputting test data;
no more than two data storage elements each holding one binary bit;
no more than two multiplexers each switching a common output between two inputs according to corresponding control signals defining multiplexor states;
interconnecting conductors between the inputs, outputs, data storage elements, and multiplexers so that the multiplexers may be switched to:
(a) connect the functional input to the first data storage element;
(b) connect the functional output to the second data storage element;
(c) connect a first of the test data inputs to a first of the test data outputs through the first data storage element; and
(d) connect a second of the test data inputs to a second of the test data outputs through the second data storage element.
2. The wrapper cells of claim 1 wherein the connections of (a) and (b) may be formed in a first single state of the multiplexers and the connections of (c) and (d) may be formed in a second single state of the multiplexers different than the first single state.
3. The wrapper cells of claim 1
wherein the functional input is received by one input of each of the two multiplexers and an output of a second multiplexer of the two multiplexers provides the first functional output;
wherein one test data input is received by the remaining input of a first multiplexer of the two multiplexers whose output is received by an input of a first memory element whose output provides a first test data output;
wherein the second test data input is received at the input of the second memory element whose output is received by remaining input of the second multiplexer of the two multiplexers and which forms the second test data output.
4. The wrapper cells of claim 1 wherein the first and second functional elements have a relationship of parent and child.
5. The wrapper cells of claim 1 wherein the plurality of wrapper cells are on both inputs and outputs of the second functional element and have identical circuitry.
6. The wrapper cells of claim 1 wherein the data storage elements are clocking flip-flops.
7. The wrapper cells of claim 1 wherein the test data inputs for at least some given wrapper cells are connected to the test data outputs of at least one of the wrapper cells and the test data outputs for the given wrapper cells are connected to the test data inputs of at least one wrapper cell.
8. An electronic computer executing a stored program to design integrated circuits having at least a first and second interconnected functional element on a substrate, the functional elements having data lines providing inputs and outputs, the stored program executing to allow placement of wrapper cells in series with data lines of the first and second functional elements, the wrapper cells comprising:
a functional input receiving an output from the first functional element;
a functional output providing an input to the second functional element;
two test data inputs each for receiving test data;
two test data outputs each for outputting test data;
no more than two data storage elements each holding one binary bit;
no more than two multiplexers each switching a common output between two inputs according to corresponding control signals defining multiplexor states;
interconnecting conductors between the inputs, outputs, data storage elements, and multiplexers so that the multiplexers may be switched to:
(a) connect the functional input to the first data storage element;
(b) connect the functional output to the second data storage element;
(c) connect a first of the test data inputs to a first of the test data outputs through the first data storage element;
(d) connect a second of the test data inputs to a second of the test data outputs through the second data storage element.
9. The wrapper cells of claim 8 wherein the connections of (a) and (b) may be formed in a first single state of the multiplexers and the connections of (c) and (d) may be formed in a second single state of the multiplexers different than the first single state.
10. The wrapper cells of claim 8
wherein the functional input is received by one input of each of the two multiplexers and an output of a second multiplexer of the two multiplexers provides the first functional output;
wherein one test data input is received by the remaining input of a first multiplexer of the two multiplexers whose output is received by an input of a first memory element whose output provides a first test data output;
wherein the second test data input is received at the input of the second memory element whose output is received by remaining input of the second multiplexer of the two multiplexers and which forms the second test data output.
11. The wrapper cells of claim 8 wherein the first and second functional elements have a relationship of parent and child.
12. The wrapper cells of claim 8 wherein the wrapper cells are on both inputs and outputs of the second functional element and have identical circuitry.
13. The wrapper cells of claim 8 wherein the data storage elements are clocking flip-flops.
14. The wrapper cells of claim 8
wherein the test data inputs for at least some given wrapper cells are connected to the test data outputs of a least one of the wrapper cell and the test data outputs for the given wrapper cells are connected to the test data inputs of at least one wrapper cell.
15. A method of manufacturing an integrated circuit having at least a first and second interconnected functional element on a substrate, the functional elements having data lines providing inputs and outputs, the method comprising the steps of:
placing a plurality of wrapper cells for integrated circuit testing in series with data lines of the first and second functional elements, the wrapper cells comprising:
a functional input receiving an output from the first functional element;
a functional output providing an input to the second functional element;
two test data inputs each for receiving test data;
two test data outputs each for outputting test data;
no more than two data storage elements each holding one binary bit;
no more than two multiplexers each switching a common output between two inputs according to corresponding control signals defining multiplexor states;
interconnecting conductors between the inputs, outputs, data storage elements, and multiplexers so that the multiplexers may be switched to:
(a) connect the functional input to the first data storage element;
(b) connect the functional output to the second data storage element;
(c) connect a first of the test data inputs to a first of the test data outputs through the first data storage element;
(d) connect a second of the test data inputs to second of the test data outputs through the second data storage element.
16. The method of claim 15 wherein the connections of (a) and (b) may be formed in a first single state of the multiplexers and the connections of (c) and (d) may be formed in a second single state of the multiplexers different than the first single state.
17. The method of claim 15
wherein the functional input is received by one input of each of the two multiplexers and an output of a second multiplexer of the two multiplexers provides the first functional output;
wherein one test data input is received by the remaining input of a first multiplexer of the two multiplexers whose output is received by an input of a first memory element whose output provides a first test data output;
wherein the second test data input is received at the input of the second memory element whose output is received by remaining input of the second multiplexer of the two multiplexers and which forms the second test data output.
18. The method of claim 15 wherein the first and second functional elements have a relationship of parent and child.
19. The method of claim 15 wherein the plurality of wrapper cells are on both inputs and outputs of the second functional elements and have identical circuitry.
20. The method of claim 15 wherein the data storage elements are clocking flip-flops.