Binary search pipeline

1. A circuit configured to perform a search for a key in a sorted list of entries using a plurality of binary search iterations, the circuit comprising:

a parallel comparison stage comprising N registers each storing a different respective one of the entries, and parallel comparison circuitry configured to compare the key to each of the entries in the N registers in parallel and generate a parallel comparison result including log 2 N bits, the parallel comparison result corresponding to log 2 N binary search iterations to search for the key in the sorted list of entries, wherein N is an integer greater than 1; and

a plurality of pipeline stages configured in a pipeline, each of the plurality of pipeline stages comprising:

memory storing an orthogonal subset of the entries relative to the subsets of the entries in memories of all others of the plurality of pipeline stages, the memory in each successive pipeline stage having exponentially more storage capacity than an immediately previous pipeline stage and including entries corresponding to a particular one of the binary search iterations; and

comparison circuitry coupled to receive the log 2 N bits from the parallel comparison stage, the comparison circuitry configured to select an entry of the memory of the pipeline stage based on a respective index including the log 2 N bits, to generate a comparison result indicating whether the key is greater than or equal to or less than the selected entry of the memory of the pipeline stage and to pass the key and the comparison result to a subsequent pipeline stage, wherein the respective index also includes a bit based on a comparison result received from a previous pipeline stage.

2. The circuit of claim 1 wherein for each of the plurality of pipeline stages, the memory of the pipeline stage is configured in several parallel slices, each slice including a unique subset of the entries in the memory.

3. The circuit of claim 2 wherein for each of the plurality of pipeline stages, the comparison circuitry of the pipeline stage is configurable to compare different size keys by combining comparisons between slices.

4. The circuit of claim 1 wherein one or more additional bits are associated with the key used by the parallel comparison stage, wherein the additional bits are used to apply additional conditions relating to processing of the key.

5. The circuit of claim 1 wherein the entries in the memory of each of the plurality of pipeline stages correspond to two consecutive binary search iterations, the circuit further comprising speculative comparison circuitry associated with each of the plurality of pipeline stages configured to compare the key to each of two entries associated with the second one of the binary search iterations that correspond to the particular entry, generate speculative comparison results corresponding to the two entries, the comparison circuitry in each memory stage also being configured to select one of the speculative comparison results based on the comparison result received from the immediately preceding memory stage.

6. The circuit of claim 1 wherein for each of the plurality of pipeline stages, the comparison circuitry of the pipeline stage is alternatively configurable to perform a prefix match comparison, an exact match comparison, or a range table comparison.

7. The circuit of claim 1 wherein for each of the plurality of pipeline stages, the memory of the pipeline stage is configured in a plurality of slices, each slice including a unique subset of the entries in the memory, and wherein the comparison circuitry in each of the plurality of pipeline stages is configurable to compare different size keys by combining comparisons between slices.

8. The circuit of claim 7 wherein each slice is configured to identify a particular one of a plurality of actions to perform on a data unit corresponding to the key, and wherein the circuit is configured to identify multiple ones of the actions for keys spanning multiple ones of the slices.

9. An integrated circuit comprising the circuit of claim 1 , wherein the integrated circuit comprises a packet switching device.

10. The integrated circuit of claim 9 wherein the packet switching device comprises an Ethernet switch.

11. At least one non-transitory computer-readable medium having data structures stored therein representative of the circuit of claim 1 .

12. The at least one non-transitory computer-readable medium of claim 11 wherein the data structures comprise a simulatable representation of the circuit.

13. The at least one non-transitory computer-readable medium of claim 12 wherein the simulatable representation comprises a netlist.

14. The at least one non-transitory computer-readable medium of claim 11 wherein the data structures comprise a code description of the circuit.

15. The at least one non-transitory computer-readable medium of claim 14 wherein the code description corresponds to a hardware description language.

16. A set of semiconductor processing masks representative of at least a portion of the circuit claim 1 .