Methods, systems, and computer readable media for next hop scaling
The subject matter described herein includes a packet forwarding device that implements next hop scaling. Rather than storing a complete set of next hop bindings at each packet processor, the storage of next hop bindings is distributed among packet processors in the packet forwarding device such that each packet processor stores next hop bindings for the hosts that are directly connected to the packet processor. For hosts that are not directly connected to a packet processor, the packet processor stores relay entries. Because of the distributed storage of next hop bindings, the number of hosts that can be served by a single packet forwarding device is increased over packet forwarding devices where each packet processor stores a complete set of next hop bindings for all connected hosts.
1. A system for address next hop scaling, the system comprising:
a packet forwarding device including:
a plurality of packet processors for performing packet forwarding operations;
a memory associated with each packet processor, the memory for storing next hop bindings for the hosts, wherein an ingress packet processor and memory associated with the ingress packet processor are configured to relay to an egress packet processor separate from the ingress packet processor a packet whose next hop is connected to the egress packet processor and wherein the egress packet processor and its memory that receive the relayed packet are configured to perform a next hop lookup to supply a destination MAC address for the packet and forward the packet to the next hop; and
wherein each memory stores a layer 3 host or layer 3 longest prefix match route table that maps IP address information to next hop information and a next hop table that maps the next hop information to layer 2 packet forwarding information.
2. The system of claim 1 wherein the memory associated with each packet processor stores relay entries for next hops connected to the remaining packet processors.
3. The system of claim 2 wherein the memory associated with each packet processor stores a single relay entry for each of the remaining packet processors.
4. The system of claim 2 wherein receipt of a packet that matched a relay entry on an ingress packet processor triggers an egress packet processor to perform an egress next hop lookup.
5. The system of claim 3 wherein the relay entries do not store MAC addresses for hosts connected to the remaining packet processors.
6. The system of claim 1 wherein the memory associated with each packet processor stores MAC addresses only for next hops that are directly connected to each packet processor such that next hop bindings for all of the hosts are distributed among the memories associated with all the packet processors.
7. The system of claim 1 wherein the available memory for the layer 3 host or longest prefix match route table and the next hop table is shared.
8. The system of claim 7 wherein each memory stores a MAC forwarding database that stores MAC and VLAN information for hosts connected to the packet forwarding device.
9. The system of claim 1 wherein the memories associated with the packet processor store next hop bindings for real and virtual hosts.
10. The system of claim 1 wherein the next hop bindings comprise address resolution protocol (ARP) bindings.
11. The system of claim 1 wherein the next hop bindings comprise IPv6 neighbor discovery bindings.
12. A method for next hop scaling, the method comprising:
distributing next hop information among memories associated with different packet processors in a packet forwarding device including a plurality of packet processors such that memories associated with different packet processors store different next hop bindings;
receiving a packet at an ingress packet processor, the packet having a next hop connected to an egress packet processor separate from the ingress packet processor;
relaying the packet to the egress packet processor;
at the egress packet processor, performing a next hop lookup to supply destination MAC information for the packet and forwarding the packet from the packet forwarding device; and
wherein each memory stores a layer 3 host or longest prefix match route table that maps IP address information to next hop information and a next hop table that maps the next hop information to layer 2 packet forwarding information.
13. The method of claim 12 wherein the memory associated with each packet processor stores relay entries for next hops connected to the remaining packet processors.
14. The method of claim 13 wherein the memory associated with each packet processor stores a single relay entry for each of the remaining packet processors.
15. The method of claim 13 wherein receipt of a packet that matched a relay entry on an ingress packet processor triggers an egress packet processor to perform an egress next hop lookup.
16. The method of claim 14 wherein the relay entries do not store MAC addresses for hosts connected to the remaining packet processors.
17. The method of claim 14 wherein the relay entries do not store MAC addresses for hosts connected to the remaining packet processors.
18. The method of claim 12 wherein the memory associated with each packet processor stores MAC addresses only for next hops that are directly connected to each packet processor such that next hop bindings for all of the hosts are distributed among the memories associated with all the packet processors.
19. The method of claim 12 wherein the available memory for the layer 3 host or longest prefix match route table and the next hop table is shared.
20. The method of claim 19 wherein each of the memory stores a MAC forwarding database that stores MAC and VLAN information for hosts connected to the packet forwarding device.
21. The method of claim 12 wherein the next hop bindings comprise address resolution protocol (ARP) bindings.
22. The method of claim 12 wherein the next hop bindings comprise IPv6 neighbor discovery bindings.
23. A non-transitory computer readable medium having stored thereon executable instructions that when executed by the processor of the computer control the computer to perform steps comprising:
distributing next hop information among memories associated with different packet processors in a packet forwarding device including a plurality of packet processors such that memories associated with different packet processors store different next hop bindings;
receiving a packet at an ingress packet processor, the packet having a next hop connected to an egress packet processor separate from the ingress packet processor;
relaying the packet to the egress packet processor;
at the egress packet processor, performing a next hop lookup to supply destination MAC information for the packet and forwarding the packet from the packet forwarding device; and
wherein each memory stores a layer 3 host or layer 3 longest prefix match route table that maps IP address information to next hop information and a next hop table that maps the next hop information to layer 2 packet forwarding information.