Memory devices and formation methods
View Patent ↗A method includes forming an electrical insulator material over an integrated circuit having a metal-containing conductive interconnect and activating a dopant in a semiconductor material of a substrate to provide a doped region. The doped region provides a junction of opposite conductivity types. After activating the dopant, the substrate is bonded to the insulator material and at least some of the substrate is removed where bonded to the insulator material. After the removing, a memory cell is formed having a word line, an access diode, a state-changeable memory element containing chalcogenide phase change material, and a bit line all electrically connected in series, the access diode containing the junction as a p-n junction. A memory device includes an adhesion material over the insulator material and bonding the word line to the insulator material.
1. A memory device comprising:
an integrated circuit having a metal-containing conductive interconnect;
an electrical insulator material over the integrated circuit;
a memory cell having a word line, an access diode above the word line, a state-changeable memory element above the access diode and containing chalcogenide phase change material, and a bit line above the memory element all electrically connected in series, the access diode containing a p-n junction in a semiconductor material, the bit line and the word line overlapping at a cross-point, and the access diode and memory element extending between the word line and the bit line at the cross-point; and
an adhesion material over the insulator material and bonding the word line to the insulator material.
2. The device of claim 1 wherein the integrated circuit comprises a structure selected from the group consisting of a memory array, a peripheral circuit, a central processing unit, an application-specific integrated circuit, a field-programmable gate array, and combinations thereof.
3. The device of claim 1 wherein the integrated circuit comprises a peripheral circuit configured to operate the memory cell formed thereover.
4. The device of claim 1 wherein the adhesion material comprises one or more metal films, an organic nanoglue, or combinations thereof.
5. The device of claim 1 wherein the adhesion material is electrically conductive and is configured to provide conductive strapping along the word line.
6. The device of claim 1 wherein the integrated circuit comprises another memory cell having another word line, another access diode, another state-changeable memory element containing chalcogenide phase change material, and another bit line all electrically connected in series, the other bit line and the other word line overlapping at another cross-point and the other access diode and other memory element extending between the other word line and the other bit line at the other cross-point.
7. The device of claim 1 wherein the insulator material is selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.
8. The device of claim 1 wherein the interconnect exhibits properties such that, if exposed to at least one operating condition used in dopant activation, a physical structure of the interconnect would be altered.
9. The device of claim 8 wherein the at least one operating condition comprises heating to greater than 400° C.
10. The device of claim 1 wherein the semiconductor material comprises a monocrystalline material and the p-n junction lies within the monocrystalline material.
11. The device of claim 1 wherein the semiconductor material comprises monocrystalline silicon exhibiting p-type conductivity.
12. The device of claim 1 wherein the bit line and the word line extend in directions orthogonal to one another.
13. A memory device comprising:
an integrated circuit including a first memory cell having a first word line, a first access diode, a first state-changeable memory element containing chalcogenide phase change material, and a first bit line all electrically connected in series, the first bit line and the first word line overlapping at a first cross-point, the access diode and memory element extending between the first word line and the first bit line at the first cross-point, and the first memory cell also having a metal-containing conductive interconnect;
an electrical insulator material over the integrated circuit;
a second memory cell having a second word line, a second access diode above the second word line, a second state-changeable memory element above the second access diode and containing chalcogenide phase change material, and a second bit line above the second memory element all electrically connected in series, the second access diode containing a p-n junction in a monocrystalline semiconductor material, the second bit line and the second word line overlapping at a second cross-point, and the second access diode and second memory element extending between the second word line and the second bit line at the second cross-point; and
an electrically conductive adhesion material over the insulator material and bonding the second word line to the insulator material and being configured to provide conductive strapping along the second word line.
14. The device of claim 13 wherein the insulator material is selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.
15. The device of claim 13 wherein the interconnect exhibits properties such that, if exposed to at least one operating condition used in dopant activation, a physical structure of the interconnect would be altered.
16. The device of claim 15 wherein the at least one operating condition comprises heating to greater than 400° C.
17. The device of claim 13 wherein the second bit line and the second word line extend in directions orthogonal to one another.
18. The device of claim 13 wherein the first bit line and the first word line extend in directions orthogonal to one another.
19. A memory device comprising:
an integrated circuit including a first memory cell having a first word line, a first access diode, a first state-changeable memory element containing chalcogenide phase change material, and a first bit line all electrically connected in series, the first bit line and the first word line overlapping at a first cross-point, the access diode and memory element extending between the first word line and the first bit line at the first cross-point, the first bit line and the first word line extending in directions orthogonal to one another, and the first memory cell also having a metal-containing conductive interconnect exhibiting properties such that, if exposed to heating to greater than 400° C., a physical structure of the interconnect would be altered;
an electrical insulator material over the integrated circuit;
a second memory cell having a second word line, a second access diode above the second word line, a second state-changeable memory element above the second access diode and containing chalcogenide phase change material, and a second bit line above the second memory element all electrically connected in series, the second access diode containing a p-n junction in a monocrystalline semiconductor material, the second bit line and the second word line overlapping at a second cross-point, the second bit line and the second word line extending in directions orthogonal to one another, and the second access diode and second memory element extending between the second word line and the second bit line at the second cross-point; and
the second word line being bonded to the insulator material.
20. The device of claim 19 further comprising an electrically conductive adhesion material over the insulator material bonding the second word line to the insulator material and being configured to provide conductive strapping along the second word line.
21. The device of claim 19 wherein the second word line is bonded directly to the insulator material.