IP Library Granted Patent US 8,836,431
Granted Patent B2
US 8,836,431 · App. 12/952,620 · Granted Sep 16, 2014

High-efficiency power amplifier with multiple power modes

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Quick Facts
Patent No.
US 8,836,431
App. No.
12/952,620
Granted
Sep 16, 2014
Kind
B2
Abstract

In a representative embodiment, a multiple mode power amplifier that is operable in a first power mode and a second power mode. The multiple mode power amplifier comprises a first amplifying unit; a second amplifying unit; a first impedance matching network connected to an output port of the first amplifying unit; a second impedance matching network connected to an output port of the second amplifying unit and to the first impedance matching network; and a third impedance matching network connected to the output ports of the first and the second amplifying units. The third impedance matching network reduces a phase difference between signals amplified by the first and the second amplifying units in the first mode.

Claims (34)

1. A multiple mode power amplifier that is operable in a first active power mode and a second active power mode, the multiple mode power amplifier comprising:

a first amplifying unit;

a second amplifying unit;

a first impedance matching network connected to an output port of the first amplifying unit;

a second impedance matching network connected to an output port of the second amplifying unit and to the first impedance matching network; and

a third impedance matching network connected to the output ports of the first and the second amplifying units, and wherein the third impedance matching network reduces a phase difference between signals amplified by the first and the second amplifying units in the first active power mode.

2. An integrated circuit comprising the power amplifier of claim 1 .

3. A wireless communication device comprising the power amplifier of claim 1 .

4. A multiple mode power amplifier that is operable in a first active power mode and a second active power mode, the multiple mode power amplifier comprising;

a first amplifying unit configured to provide a higher impedance when deactivated than when activated;

a second amplifying unit;

a first impedance matching network connected to an output port of the first amplifying unit;

a second impedance matching network connected to an output port of the second amplifying unit and to the first impedance matching network; and

a third impedance matching network connected to the output ports of the first and the second amplifying units, wherein the third impedance matching network reduces a phase difference between signals amplified by the first and the second amplifying units in the first active power mode.

5. The power amplifier of claim 4 , wherein the third impedance matching network comprises a capacitor.

6. The power amplifier of claim 5 , wherein when the power amplifier operates in the second mode, a capacitance of the capacitor is determined such that an impedance between the output port of the second amplifying unit and the other end of the second impedance matching network is higher than that of the second impedance matching network itself.

7. The power amplifier of claim 4 , wherein each of the first and the second impedance matching networks includes a bonding wire.

8. The power amplifier of claim 7 , wherein an inductance of each of the bonding wires ranges from about 0.2 to 0.4 nH.

9. The power amplifier of claim 4 , wherein a maximum output power of the first amplifying unit is greater than that of the second amplifying unit.

10. The power amplifier of claim 9 , wherein the maximum output power of the first amplifying unit is 10 times greater than that of the second amplifying unit.

11. A multiple mode power amplifier that is operable in a first power mode and a second power mode, the multiple mode power comprising:

a first amplifying unit;

a second amplifying unit;

a first impedance matching network connected to an output port of the first amplifying unit;

a second impedance matching network connected to an output port of the second amplifying unit and to the first impedance matching network;

a third impedance matching network connected to the output ports of the first and the second amplifying units; and

a control unit configured to selectively activate or deactivate the first and/or the second amplifying unit depending on a power mode of the power amplifier, wherein the third impedance matching network reduces a phase difference between signals amplified by the first and the second amplifying units in the first mode.

12. The power amplifier of claim 11 , wherein the third impedance matching network comprises a capacitor.

13. The power amplifier of claim 12 , wherein when the power amplifier operates in the second mode, a capacitance of the capacitor is determined such that an impedance between the output port of the second amplifying unit and the other end of the second impedance matching network is higher than that of the second impedance matching network itself.

14. The power amplifier of claim 11 , wherein each of the first and the second impedance matching networks includes a bonding wire.

15. The power amplifier of claim 11 , wherein a maximum output power of the first amplifying unit is greater than that of the second amplifying unit.

16. The power amplifier of claim 15 , wherein the maximum output power of the first amplifying unit is 10 times greater than that of the second amplifying unit.

17. An integrated circuit comprising the power amplifier of claim 11 .

18. A wireless communication device comprising the power amplifier of claim 11 .

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER IN THE INCORRECT US PATENT NO. 8,876,094 PREVIOUSLY RECORDED ON REEL 047351 FRAME 0384. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 8, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 049248/0558 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF THE MERGER PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0910. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047351/0384 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0910 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032851-0001) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 037689/0001 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032851/0001 →
MERGER Recorded May 7, 2013
From: AVAGO TECHNOLOGIES WIRELESS IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 030369/0471 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 23, 2010
From: HAN, CHOONG SOO; OH, JUNG MIN; JUNG, SANG HWA
To: AVAGO TECHNOLOGIES WIRELESS IP (SINGAPORE) PTE. LTD.
Reel/Frame 025397/0874 →