IP Library › Patent Application 12953055
Patent Application
App. No. 12/953,055

Configurable Processor Module Accelerator Using A Programmable Logic Device

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Quick Facts
Patent No.
US None
App. No.
12/953,055
Abstract

A configurable processor module accelerator using a programmable logic device is described. According to one embodiment, the accelerator module includes a circuit board having coupled thereto a first programmable logic device, a controller, and a first memory. The first programmable logic device has access to a bitstream which is stored in the first memory. Access to the bitstream by the first programmable logic device is controlled by the controller. The bitstream is capable of being instantiated in the first programmable logic device using programmable logic thereof to provide at least a transport interface for communication between the first programmable logic device and one or more other devices associated with the motherboard using the microprocessor interface.

Claims (11)

1 . An accelerator module, comprising:

first programmable logic device having access to a bitstream;

the bitstream capable of being stored in a first memory;

the access by the first programmable logic device to the bitstream being controlled by a controller;

the bitstream to provide a transport interface for communication between the first programmable logic device and another device using a microprocessor interface; and

the transport interface capable of direct communication via the microprocessor interface with a microprocessor located.

2 . The accelerator module according to claim 1 , wherein the controller is configured to monitor the first programmable logic device and configured to cause instantiation of the transport interface in the first programmable logic device responsive to a detected condition.

3 . The accelerator module according to claim 1 , further comprising:

a second memory; and

the bitstream capable of being instantiated in the first programmable logic device using programmable logic thereof to additionally provide a memory interface for communication with the second memory.

4 - 27 . (canceled)