SEMICONDUCTOR CHIP PACKAGES HAVING REDUCED STRESS
A structure. The structure includes (i) a carrier substrate which includes substrate pads, (ii) a chip physically attached to the carrier substrate, and (iii) a first frame physically attached to the carrier substrate. A CTE (coefficient of thermal expansion) of the first frame is substantially lower than a CTE of the carrier substrate.
1 . A structure, comprising:
a carrier substrate which includes substrate pads;
a chip physically attached to the carrier substrate; and
a first frame physically attached to the carrier substrate,
wherein a CTE (coefficient of thermal expansion) of the first frame is substantially lower than a CTE of the carrier substrate.
2 . The structure of claim 1 , wherein the CTE of the first frame is smaller than 50% of the CTE of the carrier substrate.
3 . The structure of claim 1 , wherein the CTE of the first frame is smaller than a CTE of the chip.
4 . The structure of claim 1 , further comprising a lid,
wherein the lid is in direct physical contact with the chip and the first frame such that both the chip and the first frame are sandwiched between the carrier substrate and the lid.
5 . The structure of claim 1 , wherein the CTE of the carrier substrate is in a range of 15-30 ppm/° C.
6 . The structure of claim 1 ,
wherein the first frame comprises solder balls, and
wherein the solder balls of the first frame are physically attached to the substrate pads of the carrier substrate such that at least one solder ball of the solder balls is physically attached to at least one substrate pad of the substrate pads.
7 . The structure of claim 1 , further comprising a second frame physically attached to the carrier substrate,
wherein the carrier substrate is sandwiched between the first and second frames.