IP Library Granted Patent US 8,273,643
Granted Patent B2
US 8,273,643 · App. 12/953,776 · Granted Sep 25, 2012

Diodes, and methods of forming diodes

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Quick Facts
Patent No.
US 8,273,643
App. No.
12/953,776
Granted
Sep 25, 2012
Kind
B2
Abstract

Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the least one layer. The first electrode, at least one layer, and second electrode together form a structure that conducts current between the first and second electrodes when voltage of one polarity is applied to the structure, and that inhibits current flow between the first and second electrodes when voltage having a polarity opposite to said one polarity is applied to the structure. Some embodiments include diodes having a first electrode that contains two or more projections extending upwardly from a base, having at least one layer over the first electrode, and having a second electrode over the at least one layer.

Claims (26)

1. A method of forming a diode, comprising:

forming an electrically conductive lining within an opening, the opening being bounded by electrically insulative sidewalls and by an electrically conductive bottom, the lining extending along the sidewalls and bottom to narrow the opening but not completely fill the opening;

patterning the lining into one or more pedestals; said pedestals having top surfaces, and having sidewall surfaces extending downwardly from the top surfaces;

depositing one or more layers across the top surfaces and the sidewall surfaces of the one or more pedestals;

forming an electrode over said one or more layers; and

wherein the one or more pedestals, one or more layers, and electrode together are the diode.

2. The method of claim 1 wherein the one or more layers are at least two layers.

3. The method of claim 1 wherein the one or more layers are only one layer.

4. A method of forming a diode, comprising:

forming an electrically insulative material over an electrically conductive base, the electrically insulative material having a thickness over the base;

forming an opening extending through the electrically insulative material to an upper surface of the electrically conductive base;

dispersing seed material along the upper surface of the electrically conductive base at a bottom of the opening;

growing pedestals from the dispersed seed material, the pedestals being spaced from one another by valleys, an undulating topography extending across the pedestals and valleys, the pedestals and base together being a first electrode; the pedestals having heights no greater than the thickness of the electrically insulative material;

forming one or more layers across the undulating topography;

forming a second electrode over said one or more layers; and

wherein the first electrode, one or more layers, and second electrode together are the diode.

5. The method of claim 4 wherein the dispersed seed material consists of nanocrystalline seeds.

6. The method of claim 4 further comprising forming at least one sidewall spacer along a sidewall of the opening prior to dispersing the seed material; and removing the at least one sidewall spacer after dispersing the seed material.

7. The method of claim 4 wherein the forming of the one or more layers comprises atomic layer deposition.

8. A semiconductor construction, comprising:

a first electrode supported by a semiconductor wafer, the first electrode having an undulating topography, the undulating topography comprising a lowest surface and a highest surface; the highest surface being above the lowest surface by a distance; the electrode being within an opening in an electrically insulative material; the electrically insulative material having a thickness over the semiconductor wafer and the distance between the highest and lowest surfaces being no greater than the thickness of the electrically insulative material;

one or more layers across the undulating topography, the one or more layers together having a thickness that is less than or equal to about 10% of the distance;

a second electrode over said one or more layers;

wherein the first electrode, one or more layers, and second electrode together are together a diode; and

wherein the diode is a Schottky diode.

9. The semiconductor construction of claim 8 wherein the distance is at least about 50 nanometers.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →