Design-Rule-Check Waiver
When a designer designates one or more errors identified in layout design data as false errors, waiver geometric elements corresponding to the designated false errors are created and added to the design. The waiver geometric element may be associated with a verification rule that generated its corresponding false error. When the design is subsequently analyzed using those verification rules in another verification rule check process, the waiver geometric elements are examined, and used to mask those errors associated with a waiver geometric element that would otherwise be displayed to the designer.
1 . A method of waiving an error recognized in layout design data, comprising.
identifying receiving input designating an error recognized by an electronic design automation process as a false error;
in response to receiving the input, creating a waiver item characterizing the recognized error as a false error; and
storing the waiver item for use in a subsequent electronic design automation process.
2 . The method recited in claim 1 , wherein the recognized error is a violation of a verification rule applied during the electronic design automation process verification process.
3 . The method recited in claim 2 , wherein the waiver item is associated with the verification rule.
4 . The method recited in claim 1 , wherein the waiver item is a waiver geometric element having a shape corresponding to a shape of the recognized error, such that the waiver geometric element can be used to mask the recognized error in error results displayed by the subsequent electronic design automation process.
5 . The method recited in claim 1 , further comprising:
performing the electronic design automation process at a first location; and
performing the subsequent electronic design automation process at a second location different from the first location.
6 . A method of analyzing a layout design, comprising:
performing an electronic design process on layout design data to produce analysis results including one or more errors in the layout design data;
comparing the one or more design errors with a waiver item to identify design errors corresponding to the waiver item; and
omitting identified design errors corresponding to the waiver item from the analysis results.
7 . The method recited in claim 6 , further comprising storing the omitted identified design errors separately from the analysis results.
8 . The method recited in claim 6 , wherein
the waiver item is a waiver geometric element; and
further comprising omitting the identified design errors corresponding to the waiver geometric element from the analysis results by employing a shape of the waiver geometric element to mask the identified design errors.
9 . The method recited in claim 6 , wherein the one or more errors are violations of a verification rule applied during the electronic design automation process verification process; and
the waiver item is associated with the verification rule.
10 . The method recited in claim 9 , further comprising:
comparing the one or more design errors with the waiver item by
determining a first overlap of the waiver geometric element with an identified error;
determining a second overlap of the identified error with the waiver geometric element; and
determining that the identified error corresponds with the waiver geometric element if the first overlap exceeds a first threshold amount or the second overlap exceeds a second threshold amount.
11 . The method recited in claim 10 , wherein the first threshold amount is different from the second threshold amount.
12 . The method recited in claim 9 , further comprising:
comparing the one or more design errors with the waiver item by determining a first overlap of the waiver geometric element with an identified error; and
if the waiver geometric element does not overlap the identified error by a threshold amount, determining that the identified error does not correspond with the waiver geometric element.