IP Library Granted Patent US 10,297,640
Granted Patent B2
US 10,297,640 · App. 12/955,494 · Granted May 21, 2019

Cross-point memory with self-defined memory elements

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Quick Facts
Patent No.
US 10,297,640
App. No.
12/955,494
Granted
May 21, 2019
Kind
B2
Abstract

Some embodiments include a memory device having first structures arranged in a first direction and second structures arranged in a second direction. At least one structure among the first and second structures includes a semiconductor material. The second structures contact the first structures at contact locations. A region at each of the contact locations is configured as memory element to store information based on a resistance of the region. The structures can include nanowires. Other embodiments are described.

Claims (26)

1. A memory device comprising:

a first material continuously arranged in a first direction; and

second materials, each material of the second materials continuously arranged in a second direction, at least one material among the first material and the second materials including a semiconductor material, the second materials directly contacting the first material at contact locations at memory cell regions with respect to a top view of the first and second materials, the first material contacting the memory cell regions and spanning in the first direction continuously at locations between the memory cell regions, wherein for each of the first and the second materials, a first region including a portion of one of the first material and the second materials at each of the contact locations is configured to store information based on a resistance of the first region, and a second region including a portion of the second materials directly opposite from the first region is not configured to store information; and

a third material having a first side and a second side opposite from the first side and a third side connecting the first side to the second side, and at least one second material of the second materials completely coats the first, second, and third sides, wherein the at least one second material of the second materials completely coating the first, second, and third sides includes a same resistance material, the at least one second material of the second materials has a first side and a second side opposite from the first side, and the portion of the second materials directly opposite from the first region is included in the second side of the at least one second material of the second materials, and the entire second side of the at least one second material of the second materials is not configured to store information, wherein the first material includes a length spanning in the first direction continuously at locations between the memory cell regions with respect to the top view, and each of the second materials includes a length spanning in the second direction continuously at locations between the memory cell regions with respect to the top view, and wherein a direction from the first side of the at least one second material of the second materials to the second side of the at least one second material of the second materials is perpendicular to the length of each of the second materials.

2. The memory device of claim 1 , wherein the semiconductor material is included in only the first material.

3. The memory device of claim 1 , wherein each material of the second materials includes a variable resistance material and spans in the second direction continuously at locations between the memory cell regions in the second direction.

4. The memory device of claim 1 , wherein the semiconductor material is included in the first material and has a first conductivity type, and the second materials have a second conductivity type.

5. The memory device of claim 4 , wherein at least one of the first and second materials has a circular cross-section.

6. The memory device of claim 3 , wherein the third material includes metal.

7. The memory device claim 1 , wherein the semiconductor material is included in only the second materials.

8. The memory device of claim 1 , wherein the semiconductor material is included in only the first material, and each material of the second materials includes a phase change material contacting the semiconductor material.

9. A memory device comprising:

a first semiconductor material continuously arranged in the a direction; and

second materials, each material of the second materials including a second semiconductor material continuously arranged in a second direction, and additional materials continuously arranged in the second direction, the second semiconductor material includes a first side and second side opposite from the second side and a third side connecting the first side to the second side, one of the additional materials completely coating the first, second, and third sides of the second semiconductor material of one of the second materials, the second materials crossing the first material at contact locations at memory cell regions with respect to a top view of the first and second materials, the top view being perpendicular to and a substrate of the memory device and the first and second directions, such that the additional materials directly contact the first semiconductor material at the contact locations, the first semiconductor material contacting the memory cell regions and spanning in the first direction continuously at locations between the memory cell regions, wherein for each of the first semiconductor material and the additional materials, a first region including a portion of the additional materials at each of the contact locations is configured to operate as a memory element of a memory cell of the memory device, and a second region including a portion of the additional materials directly opposite from the first region is not configured to store information, and a cross-section of the second semiconductor material of at least one of the second materials includes the first, second, and third sides, and the first, second, and third sides are surrounded by a respective additional material among the additional materials, wherein the respective additional material surrounding the first, second, and third sides of the at least one of the second materials includes a same resistance material, the respective additional material has a first side and a second side opposite from the first side, and the portion of the additional materials directly opposite from the first region is included in the second side of the respective additional material, and the entire second side of the respective additional material is not configured to store information, wherein the first material includes a length spanning in the first direction continuously at locations between the memory cell regions with respect to the top view, and each of the second materials includes a length spanning in the second direction continuously at locations between the memory cell regions with respect to the top view, and wherein a direction from the first side of the at least one second material of the second materials to the second side of the at least one second material of the second materials is perpendicular to the length of each of the second materials.

10. The memory device of claim 9 , wherein each of the additional materials includes a phase change material.

11. The memory device of claim 9 , wherein each of the additional materials includes a metal oxide material.

12. The memory device of claim 9 , wherein each of the additional materials includes a uni-polar memory switching material.

13. The memory device of claim 9 , wherein the first semiconductor material and the second semiconductor material have different conductivity types.

14. The memory device of claim 9 , wherein each of the first and second materials has a diameter of in a range of 5 nanometers to 100 nanometers.

15. A method of forming a memory device, the method comprising:

arranging a first material in a first direction; and

arranging second materials in a second direction including arranging a each material of the second materials continuously in the second direction, at least one material among the first and second materials including a semiconductor material, wherein the first and second materials are arranged such that the second materials directly contact the first material at contact locations at memory cell regions with respect to a top view of the first and second materials and such that a memory element associated with each of the contact locations is included in the material of the second structures when the second materials are formed, the top view being perpendicular to a substrate of the memory device and the first and second directions, the first material contacting the memory cell regions and spanning in the first direction continuously at locations between the memory cell regions, wherein for each of the first and the second materials, a first region associated with the memory element is configured to store information, and a second region including a portion of the second materials directly opposite from the first region is not configured to store information; and

an additional semiconductor material having a first side and a second side opposite from the first side and a third side connecting the first side to the second side, and one of the second materials completely coats the first, second, and third sides, wherein the one of the second materials completely coating the first, second, and third sides of the additional semiconductor material includes a same resistance material, the one of the second materials has a first side and a second side opposite from the first side, and the portion of the second materials directly opposite from the first region is included in the second side of the one of the second materials, and the entire second side of the one of the second materials is not configured to store information, wherein the first material includes a length spanning in the first direction continuously at locations between the memory cell regions with respect to the top view, and each of the second materials includes a length spanning in the second direction continuously at locations between the memory cell regions with respect to the top view, and wherein a direction from the first side of the at least one second material of the second materials to the second side of the at least one second material of the second materials is perpendicular to the length of each of the second materials.

16. The method of claim 15 , wherein the semiconductor material has a first conductivity type and is included in the first material, and the additional semiconductor material of a second conductivity type.

17. The method of claim 15 , wherein each material of the second materials includes a variable resistance material.

18. The method of claim 15 , wherein each material second materials includes a phase change material.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →