IP Library Granted Patent US 8,552,503
Granted Patent B2
US 8,552,503 · App. 12/957,304 · Granted Oct 8, 2013

Strained silicon structure

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Quick Facts
Patent No.
US 8,552,503
App. No.
12/957,304
Granted
Oct 8, 2013
Kind
B2
Abstract

A strained silicon substrate structure includes a first transistor and a second transistor disposed on a substrate. The first transistor includes a first gate structure and two first source/drain regions disposed at two sides of the first gate structure. A first source/drain to gate distance is between each first source/drain region and the first gate structure. The second transistor includes a second gate structure and two source/drain doped regions disposed at two side of the second gate structure. A second source/drain to gate distance is between each second source/drain region and the second gate structure. The first source/drain to gate distance is smaller than the second source/drain to gate distance.

Claims (28)

1. A strained silicon structure comprising:

a substrate having a top surface and having a low density region and a high density region;

a first transistor disposed on the top surface within the low density region, the first transistor comprising:

a first gate structure disposed on the top surface; and

a first source/drain region disposed in the substrate at one side of the first gate structure, wherein a first source/drain to gate distance is defined between the first source/drain region and the first gate structure, and the first source/drain region is stressed

wherein the first source/drain region comprise:

a first recess disposed in the substrate at one side of the substrate; and a first epitaxial layer filling the first recess; and

a second transistor disposed on the top surface within the high density region, the second transistor comprising:

a second gate structure disposed on the top surface; and

a second source/drain region disposed in the substrate at one side of the second gate structure, wherein a second source/drain to gate distance is defined between the second source/drain region and the second gate structure, the second source/drain region is stressed, and the first source/drain to gate distance is smaller than the second source/drain to gate distance.

2. The strained silicon structure of claim 1 , wherein the first recess has a first opening, and a first distance is the shortest distance between the first gate structure and the first opening.

3. The strained silicon structure of claim 2 , wherein the second source/drain region comprises:

a second recess disposed in the substrate at one side of the substrate; and

a second epitaxial layer filling the second recess.

4. The strained silicon structure of claim 3 , wherein the second recess has a second opening, and a second distance is the shortest distance between the second gate structure and the second opening.

5. The strained silicon structure of claim 4 , wherein the first distance is shorter than the second distance.

6. The strained silicon structure of claim 1 , wherein the cross-sectional profile of the first source/drain region comprises a diamond-like shape, an octagon, or a U shape.

7. The strained silicon structure of claim 1 , wherein the cross-sectional profile of the second source/drain region comprises a diamond-like shape, an octagon, or a U shape.

8. The strained silicon structure of claim 1 , wherein the first transistor comprises a logic device, a memory device or an input/output device.

9. The strained silicon structure of claim 1 , wherein the second transistor comprises a logic device, a memory device or an input/output device.

10. The strained silicon structure of claim 1 , further comprising:

a first channel disposed under the first gate structure; and

a second channel disposed under the second structure, wherein a strain in the first channel is greater than a strain in the second channel.

11. The strained silicon structure of claim 1 , wherein the first transistor and the second transistor have a same conductivity type.

12. The strained silicon structure of claim 1 , further comprising:

a first epitaxial layer disposed within the first source/drain region; and

a second epitaxial layer disposed within the second source/drain region,

wherein the first epitaxial layer and the second epitaxial have a same composition.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 30, 2010
From: HWANG, GUANG-YAW; CHOU, LING-CHUN; WANG, I-CHANG; HUANG, SHIN-CHUAN; LIAO, JIUNN-HSIUNG; CHEN, SHIN-CHI; LIN, PAU-CHUNG; YEH, CHIU-HSIEN; CHIEN, CHIN-CHENG; CHEN, CHIEH-TE
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 025403/0994 →