IP Library › Granted Patent US 8,482,005
Granted Patent B2
US 8,482,005 · App. 12/957,772 · Granted Jul 9, 2013

Display device comprising an oxide semiconductor layer

Inventors: Shunpei Yamazaki (Setagaya, JP); Hajime Kimura (Atsugi, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
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Quick Facts
Patent No.
US 8,482,005
App. No.
12/957,772
Granted
Jul 9, 2013
Kind
B2
Abstract

The time taken to write a signal to a pixel is shortened in a display device. Further, a signal is written at high speed even when high voltage is applied. The display device includes a pixel including a transistor and a liquid crystal element electrically connected to a source or a drain of the transistor. The transistor includes an intrinsic or substantially intrinsic oxide semiconductor as a semiconductor material and has an off-state current of 1×10 −17 A/μm or less. The pixel does not include a capacitor. Since it is not necessary to provide a capacitor, the time taken to write a signal can be shortened.

Claims (72)

1. A display device comprising:

a pixel, the pixel comprising:

a transistor; and

a liquid crystal element,

wherein the liquid crystal element is electrically connected to one of a source and a drain of the transistor,

wherein the transistor includes an intrinsic or substantially intrinsic oxide semiconductor layer which includes a channel formation region,

wherein an off-state current of the transistor is 1×10 −17 A/μm or less, and

wherein the pixel does not include a capacitor wiring.

2. The display device according to claim 1 , wherein a voltage higher than or equal to a voltage of a video signal is input to the liquid crystal element before the video signal is input.

3. A display device comprising:

a pixel, the pixel comprising:

a transistor; and

a liquid crystal element,

wherein the liquid crystal element is electrically connected to one of a source and a drain of the transistor,

wherein the transistor includes an intrinsic or substantially intrinsic oxide semiconductor layer which includes a channel formation region,

wherein an off-state current of the transistor is 1×10 −17 A/μm or less,

wherein the pixel does not include a capacitor wiring, and

wherein a parasitic capacitance in the pixel is less than or equal to 50 fF.

4. The display device according to claim 3 , wherein a voltage higher than or equal to a voltage of a video signal is input to the liquid crystal element before the video signal is input.

5. A display device comprising:

a pixel, the pixel comprising:

a first electrode;

a second electrode, the second electrode comprising a portion not overlapping with the first electrode;

an insulating film between the first electrode and the second electrode;

a transistor; and

a liquid crystal layer,

wherein the liquid crystal layer is over the first electrode and the second electrode,

wherein the second electrode is electrically connected to one of a source and a drain of the transistor,

wherein the transistor includes an intrinsic or substantially intrinsic oxide semiconductor layer which includes a channel formation region,

wherein an off-state current of the transistor is 1×10 ˜ 17 A/μm or less, and

wherein the pixel does not include a capacitor wiring.

6. The display device according to claim 5 , wherein a voltage higher than or equal to a voltage of a video signal is input to the first electrode before the video signal is input.

7. The display device according to claim 5 , wherein the second electrode is over the first electrode.

8. The display device according to claim 5 , wherein the first electrode and the second electrode do not overlap with each other.

9. A display device comprising:

a pixel, the pixel comprising:

a first electrode;

a second electrode, the second electrode comprising a portion not overlapping with the first electrode;

an insulating film between the first electrode and the second electrode;

a transistor; and

a liquid crystal layer,

wherein the liquid crystal layer is over the first electrode and the second electrode,

wherein the second electrode is electrically connected to one of a source and a drain of the transistor,

wherein the transistor includes an intrinsic or substantially intrinsic oxide semiconductor layer which includes a channel formation region,

wherein an off-state current of the transistor is 1×10 −17 A/μm or less,

wherein the pixel does not include a capacitor wiring, and

wherein a parasitic capacitance in the pixel is less than or equal to 50 fF.

10. The display device according to claim 9 , wherein a voltage higher than or equal to a voltage of a video signal is input to the first electrode before the video signal is input.

11. The display device according to claim 9 , wherein the second electrode is over the first electrode.

12. The display device according to claim 9 , wherein the first electrode and the second electrode do not overlap with each other.

13. A display device comprising:

a pixel, the pixel comprising:

a transistor; and

a liquid crystal element,

wherein the liquid crystal element is electrically connected to one of a source and a drain of the transistor,

wherein the transistor includes an oxide semiconductor layer including a channel formation region,

wherein the oxide semiconductor layer comprises a portion in which a concentration of hydrogen is 5×10 19 /cm 3 or lower,

wherein an off-state current of the transistor is 1×10 −17 A/μm or less, and

wherein the pixel does not include a capacitor wiring.

14. The display device according to claim 13 , wherein a voltage higher than or equal to a voltage of a video signal is input to the liquid crystal element before the video signal is input.

15. The display device according to claim 13 , wherein a parasitic capacitance in the pixel is less than or equal to 50 fF.

16. A display device comprising:

a pixel, the pixel comprising:

a transistor; and

a liquid crystal element,

wherein the liquid crystal element is electrically connected to one of a source and a drain of the transistor,

wherein the transistor includes an oxide semiconductor layer including a channel formation region,

wherein the oxide semiconductor layer comprises a portion in which a carrier concentration is 1×10 12 /cm 3 or lower,

wherein an off-state current of the transistor is 1×10 −17 A/μm or less, and

wherein the pixel does not include a capacitor wiring.

17. The display device according to claim 16 , wherein a voltage higher than or equal to a voltage of a video signal is input to the liquid crystal element before the video signal is input.

18. The display device according to claim 16 , wherein a parasitic capacitance in the pixel is less than or equal to 50 fF.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 1, 2010
From: YAMAZAKI, SHUNPEI; KIMURA, HAJIME
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 025415/0400 →
Priority Claims (1)
JP 2009-276374 · Dec 4, 2009 · national
Continuity (1)
Related Publication 20110134345A1 · Jun 9, 2011