System for wafer-level phosphor deposition

1. A method for phosphor deposition on a semiconductor wafer, the method comprising:

depositing a semiconductor wafer having a plurality of light emitting diode (“LED”) dies on a carrier wafer;

covering a first surface of the semiconductor wafer with a photo resist material layer having a first height;

removing at least a portion of the photo resist material layer to expose at least a portion of the semiconductor wafer and preserving remaining photo resist material layer to form a plurality of posts having the first height covering electrical contacts associated with the plurality of LED dies from exposure, wherein preserving remaining photo resist material layer to form a plurality of posts includes substantially aligning bottom surfaces of the plurality of posts in a first plain, wherein no post has a bottom surface in a plain different than the first plain;

depositing a phosphor layer with a substantial uniform thickness having a second height only on the exposed portions of the semiconductor wafer and allowing the second height of phosphor layer to be lower than the first height of the plurality of posts, and allowing a portion of the phosphor layer to contact at least part of circumference of one of the plurality of posts, wherein depositing the phosphor layer includes allowing bottom surface of the phosphor layer to be substantially aligned; and

removing the remaining photo resist material after depositing the phosphor to expose the electrical contacts.

2. The method of claim 1 , further comprising performing a singulation process to cut the plurality of LED dies from the semiconductor wafer to form individual dies.

3. The method of claim 1 , further comprising probing the electrical contacts to determine a plurality of color temperatures associated with the plurality of LED dies, respectively.

4. The method of claim 3 , further comprising mapping the plurality of color temperatures to X and Y values associated with a color chart.

5. The method of claim 4 , further comprising performing a singulation process to cut the plurality of LED dies from the semiconductor wafer to form individual dies each having an associated X and Y value.

6. The method of claim 5 , further comprising:

identifying one or more bins in a binning table, wherein each bin comprises a range of X and Y values; and

sorting the individual dies based on their associated X and Y values according to the binning table.

7. The method of claim 1 , further comprising attaching a carrier wafer to support the semiconductor wafer.

8. The method of claim 7 , wherein attaching a carrier wafer to support the semiconductor wafer includes applying a thermal release tape between the carrier wafer and the semiconductor wafer.

9. The method of claim 8 , wherein removing the carrier wafer includes heating the thermal release tape to separate the carrier wafer from the semiconductor wafer.

10. The method of claim 7 , wherein the carrier wafer includes sapphire wafer.

11. A method for depositing a phosphor layer comprising:

depositing a semiconductor wafer containing a plurality of light emitting diode (“LED”) dies on a carrier wafer;

depositing a photo resist material layer having a first height over the semiconductor wafer;

removing portions of the photo resist material layer to expose portions of the semiconductor wafer and allowing remaining portion of the photo resist material layer to form at least one post with the first height covering over an electrical contact associated with one of the plurality of LED dies, wherein allowing remaining portion of the photo resist material layer includes substantially aligning bottom surface of the remaining portion of the photo resist material layer in a first plan, wherein no remaining portion of the photo resist material layer has a bottom surface in a plain different than the first plain;

depositing a phosphor layer with a substantial uniform thickness having a second height only on the exposed portions of the semiconductor wafer, wherein depositing the phosphor layer includes substantially aligning bottom surface of the phosphor layer;

allowing at least a portion of the phosphor layer to contact at least part of circumference of one of the plurality of posts and allowing the first height of the photo resist material layer to be higher than the second height of the phosphor layer so that the phosphor layer forms around the post; and

removing the remaining portion of the photo resist material to expose the electrical contacts.

12. The method of claim 11 , further comprising energizing each of the plurality of LED dies in the semiconductor wafer to determine a color temperature.

13. The method of claim 12 , further comprising mapping the color temperature with color temperature chart of the plurality of LED dies.

14. The method of claim 13 , further comprising identifying number of bins arranged in X and Y values of a color temperature chart.

15. The method of claim 14 , further comprising sorting the plurality of the LED dies into different bins in accordance with X and Y values during a wafer singulation process.

16. The method of claim 15 , wherein sorting the plurality of the LED dies into different bins includes performing a dicing process to separate the plurality of LED dies from the semiconductor wafer.

17. The method of claim 11 , further comprising performing a singulation process to separate the plurality of LED dies from the semiconductor wafer to form individual dies.

18. The method of claim 11 , wherein allowing the predefined first thickness of photo resist material to be thicker than the predefined second thickness of the phosphor layer includes forming the post having a range of thickness between 100 and 500 micrometers.