System for wafer-level phosphor deposition
View Patent ↗System for wafer-level phosphor deposition. In an aspect, a semiconductor wafer is provided that includes a plurality of LED dies wherein at least one die includes an electrical contact, a photo-resist post covering the electrical contact, and a phosphor deposition layer covering the semiconductor wafer and surrounding the photo-resist post. In another aspect, a semiconductor wafer is provided that comprises a plurality of LED dies wherein at least one die comprises an electrical contact, a phosphor deposition layer covering the semiconductor wafer, and a cavity in the phosphor deposition layer exposing the at least one electrical contact.
1. A semiconductor wafer comprising:
a thermal release tape disposed over a carrier wafer;
the semiconductor wafer disposed over the thermal release tape;
a plurality of LED dies fabricated on the semiconductor wafer, wherein at least one die comprises at least one electrical contact;
at least one photo-resist post, having a first end, a second end, and a body with a first height, wherein the first end is situated at a top of the body and the second end is situated at a base of the body, wherein the second end of the at least one photo-resist post is disposed over the at least one electrical contact; and
a phosphor deposition layer having a thickness with a second height covering the semiconductor wafer and surrounding a circumference of the at least one photo-resist post, wherein the first height of the body of the at least one photo-resist post is higher than the second height of the thickness of the phosphor deposition layer.
2. The semiconductor wafer of claim 1 , wherein the at least one photo-resist post is approximately 200 micrometers in height.
3. The semiconductor wafer of claim 1 , wherein the photo-resist post has a shape configured to cover the at least one electrical contact.
4. The semiconductor wafer of claim 1 , wherein the semiconductor wafer is approximately 150 micrometers thick.
5. The semiconductor wafer of claim 1 , wherein the carrier wafer includes a sapphire wafer.
6. A semiconductor wafer comprising:
a thermal release tape disposed over a sapphire carrier wafer;
an LED semiconductor wafer having a top surface and a base surface, the base surface of the LED semiconductor wafer disposed over the thermal release tape;
a plurality of LED dies fabricated on the top surface of the LED semiconductor wafer, wherein at least one die comprises at least one p-type electrical contact and one n-type electrical contact;
a phosphor deposition layer covering the semiconductor wafer wherein thickness of the phosphor deposition layer is lower than thickness of at least one removable photo-resist post; and
at least one cavity in the phosphor deposition layer, resulting from removing said at least one removable photo-resist post, exposing the at least one n-type electrical contact and another cavity in the phosphor deposition layer exposing the at least one p-type electrical contact.
7. The semiconductor wafer of claim 6 , wherein each of the plurality of LED dies includes borders between neighboring LED dies for a singulation process.
8. The semiconductor wafer of claim 7 , further comprising embedded wires near the top surface of LED semiconductor wafer for conducting current for the at least one p-type electrical contact.
9. The semiconductor wafer of claim 6 , wherein the semiconductor wafer is approximately 150 micrometers thick.