IP Library › Granted Patent US 8,473,439
Granted Patent B2
US 8,473,439 · App. 12/963,558 · Granted Jun 25, 2013

Integrate and fire electronic neurons

Inventors: John V. Arthur (Mountain View, CA); Gregory S. Corrado (San Francisco, CA); Steven K. Esser (San Jose, CA); Paul A. Merolla (Palo Alto, CA); Dharmendra S. Modha (San Jose, CA)
Assignee: International Business Machines Corporation
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Quick Facts
Patent No.
US 8,473,439
App. No.
12/963,558
Granted
Jun 25, 2013
Kind
B2
Abstract

An integrate and fire electronic neuron is disclosed. Upon receiving an external spike signal, a digital membrane potential of the electronic neuron is updated based on the external spike signal. The electric potential of the membrane is decayed based on a leak rate. Upon the electric potential of the membrane exceeding a threshold, a spike signal is generated.

Claims (74)

1. A method, comprising:

in response to an external spike signal in an integrate and fire electronic neuron, updating a digital membrane potential based on the external spike signal, wherein the digital membrane potential represents a neuron membrane potential;

decaying the digital membrane potential based on a leak rate; and

upon the digital membrane potential exceeding a threshold, generating a spike signal.

2. The method of claim 1 , wherein updating the membrane potential comprises:

upon receiving external excitatory spike signals, increasing the membrane potential by an increment equal to the number of excitatory spike signals received in a time step, multiplied by a first scaling parameter; and

upon receiving external inhibitory spike signals, decreasing the membrane potential by a decrement equal to the number of inhibitory spike signals received in a time step, multiplied by a second scaling parameter.

3. The method of claim 2 , wherein:

the first scaling parameter is a multiple of 2, such that multiplication of the number of the received excitatory spikes by the scaling factor is performed by a digital bit shift operation.

4. The method of claim 2 , wherein:

the second scaling parameter is a multiple of 2, such that multiplication of the number of the received excitatory spikes by the scaling factor is performed by a digital bit shift operation.

5. The method of claim 4 , wherein:

decaying the membrane potential comprises decaying the membrane potential based on a leak rate equal to a current value of the membrane potential divided by a time constant.

6. The method of claim 5 , wherein:

the time constant is a multiple of 2 such that dividing the membrane potential by the time constant value is performed by a digital bit shift-operation.

7. The method of claim 4 , wherein:

updating the membrane potential comprises, upon receiving an inhibitory spike signal, increasing an inhibitory channel conductance value.

8. The method of claim 7 further comprising:

decaying the inhibitory channel conductance value based on a leak rate equal to a current value of the inhibitory channel conductance value divided by a time constant, wherein the time constant is a multiple 2 such that dividing the inhibitory channel conductance value by the time constant is performed by a bit shift-operation; and

applying inhibition into the membrane potential by decreasing the membrane potential based on the inhibitory channel conductance value.

9. The method of claim 8 , wherein:

applying inhibition into the membrane potential comprises subtracting from the membrane potential a current value of the membrane potential value divided by a divisor value, wherein the divisor value comprises 2 to a power equal to a scaling factor minus the most significant non-zero bit in the inhibitory channel conductance value.

10. The method of claim 4 , further comprising:

modeling synaptic channel conductance in the electronic neuron as a difference of two inhibitory channel conductance variables which increase by a strength factor with each external spike signal; and

decaying the conductance variables based on a decay rate governed by a time constant, wherein the time constant is a multiple of 2 such that the decay is performed through a digital bit shift operation.

11. The method of claim 10 , further comprising:

applying inhibition into the membrane potential by subtracting from the membrane potential a current value of the membrane potential divided by a divisor value, wherein the divisor value is 2 to a power equal to a scaling factor minus the most significant non-zero bit in the value of the difference of the inhibitory channel conductance variables; and

applying excitation into the membrane potential by adding a membrane potential complement value to an excitatory strength shift factor using a bit shift operation to generate a sum, and dividing the sum by a divisor that is 2 to a power equal to a scaling factor minus the most significant non zero bit in the value of the difference of the excitatory channel conductance variables.

12. An integrate and fire electronic neuron, comprising:

a digital counter representing a membrane potential of the neuron;

a controller configured for updating the membrane potential based on external spike signals, by:

upon receiving an external excitatory spike signal, incrementing the membrane potential by an increment using bit-wise operations such that only bits in the counter that need change are modified; and

upon receiving an external inhibitory spike signal, decrementing the membrane potential by a decrement using bit-wise operations such that only bits in the counter that need change are modified;

a decay module configured for decaying the membrane potential based on a time constant using an analog resistor-capacitor model; and

a spiking module configured for, upon the membrane potential exceeding a threshold, generating a spike signal.

13. The integrate and fire electronic neuron of claim 12 , wherein:

the decay module is configured for decaying the membrane potential by generating decay events based on a time constant using an analog resistor-capacitor model.

14. The integrate and fire electronic neuron of claim 13 , wherein:

when a decay event occurs, if most-significant-bit of the counter is one, the most-significant-bit of the counter is set to zero, otherwise all lower-order bits of the counter are set to zero.

15. The integrate and fire electronic neuron of claim 14 , wherein:

when the neuron generates a spike signal, the capacitor is quickly discharged, and charged at a charging rate, and upon the charge reaching a threshold, a decay event is generated.

16. The integrate and fire electronic neuron of claim 14 , wherein:

when the neuron generates a spike signal, the capacitor is quickly discharged, and charged at a charging rate, and upon the charge reaching a first threshold, a decay event is generated; and

the capacitor is discharged at a rate, and upon the charge reaching a second threshold, a decay event is generated.

17. The integrate and fire electronic neuron of claim 13 , wherein:

the resistor-capacitor model comprises two capacitors; and

the electric potential of the membrane is decayed by:

when the neuron generates a first spike signal, quickly discharging a first capacitor while switching to a second capacitor; and

when the neuron generates a second spike signal, quickly discharging the second capacitor while switching to the first capacitor.

18. A method, comprising:

upon receiving an external spike signal in an event driven integrate and fire electronic neuron, updating a digital membrane potential of an electronic neuron based on the external spike signal;

decaying the membrane potential based on a leak rate; and

upon the membrane potential exceeding a threshold, generating a spike signal;

wherein, updating the membrane potential further comprises, when an excitatory event type occurs, incrementing the membrane potential by an excitatory synaptic strength increment.

19. The method of claim 18 , wherein:

updating the membrane potential further comprises, when an inhibitory event type occurs, decrementing the membrane potential by an inhibitory synaptic strength decrement.

20. The method of claim 19 , wherein:

updating the membrane potential further comprises, when a decay event type occurs, decrementing the membrane potential by a leak strength decrement.

21. The method of claim 20 , wherein:

generating a spike signal further comprises setting the membrane potential to a reset value.

22. The method of claim 18 , wherein:

in response to a decay event occurring, the neuron transmitting a spike event if the membrane potential is above threshold, maintaining simulation and hardware correspondence.

23. An integrate and fire electronic neuron, comprising:

a digital membrane potential counter;

a controller module configured for, in response to an external spike signal in an integrate and fire electronic neuron, updating a digital membrane potential based on the external spike signal, wherein the digital membrane potential represents a neuron membrane potential;

a decay module configured for decaying the digital membrane potential based on a leak rate; and

a spiking module configured for, upon the digital membrane potential exceeding a threshold, generating a spike signal.

24. The integrate and fire electronic neuron of claim 23 , wherein:

the controller module is further configured for updating the membrane potential by:

upon receiving external excitatory spike signals, increasing the membrane potential by an increment equal to the number of excitatory spike signals received in a time step, multiplied by a first scaling parameter; and

upon receiving external inhibitory spike signals, decreasing the membrane potential by a decrement equal to the number of inhibitory spike signals received in a time step, multiplied by a second scaling parameter.

25. The integrate and fire electronic neuron of claim 24 , wherein:

the first scaling parameter is a multiple of 2, such that multiplication of the number of the received excitatory spikes by the scaling factor is performed by a digital bit shift operation; and

the second scaling parameter is a multiple of 2, such that multiplication of the number of the received excitatory spikes by the scaling factor is performed by a digital bit shift operation.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 8, 2010
From: ARTHUR, JOHN V.; CORRADO, GREGORY S.; ESSER, STEVEN K.; MEROLLA, PAUL A.; MODHA, DHARMENDRA S.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 025468/0152 →
Continuity (1)
Related Publication 20120150781A1 · Jun 14, 2012