TCP receiver acceleration
A method for processing network information may include performing by one or more processors and/or circuits integrated within a single chip, classifying a header portion of a received packet based on connection context information within the received packet. The connection context information may be acquired by the single chip from a memory external to the single chip. The connection context information for the received packet may be updated based on the classifying. At least a payload portion of the received packet may be communicated to a destination, based on the updated connection context information. The classifying, updating and communicating may be performed asynchronously. The header portion of the received packet may be parsed and/or validated. The connection context information of the received packet may be evaluated.
1. A method for processing network information, the method comprising:
classifying, by a processor integrated within a single chip, a header portion of a received packet based on connection context information within said received packet, wherein said connection context information is acquired by said single chip from a memory external to said single chip;
updating, by said processor, said connection context information for said received packet based on said classifying; and
communicating, by said processor, at least a payload portion of said received packet to a destination, based on said updated connection context information.
2. The method according to claim 1 , wherein said classifying, updating and communicating are performed asynchronously.
3. The method according to claim 1 , comprising parsing said header portion of said received packet.
4. The method according to claim 1 , comprising validating said header portion of said received packet.
5. The method according to claim 1 , comprising evaluating said connection context information of said received packet.
6. The method according to claim 1 , comprising evaluating said updated connection context information.
7. The method according to claim 1 , comprising executing said classifying during a first processing stage.
8. The method according to claim 1 , comprising executing said classifying at a first processing stage during a first period of time.
9. The method according to claim 8 , comprising executing said updating at a second processing stage during a second period of time, said second period of time independent of said first period of time.
10. The method according to claim 1 , wherein said connection context information is for an established connection.
11. The method according to claim 10 , wherein said memory comprises fast access memory.
12. The method according to claim 1 , comprising determining based on said connection context information, whether said received packet is marked for hardware acceleration processing.
13. The method according to claim 12 , comprising if said received packet is marked for said hardware acceleration processing, accelerating processing of said received packet.
14. The method according to claim 12 , comprising, if said received packet is not marked for said hardware acceleration processing, passing said received packet to a host processor for non-accelerated processing in software.
15. The method according to claim 1 , comprising identifying whether a connection is to be removed based on one or more of said connection context information or said updated connection context information.
16. The method according to claim 15 , comprising, if said connection is to be removed, instructing a synchronization module integrated within said single chip to remove said connection.
17. The method according to claim 1 , wherein said classifying is performed by one or more of an analysis engine or at least one reduced instruction set computer (RISC) processor.
18. The method according to claim 1 , wherein said updating is performed by one or more of a context processing engine or at least one reduced instruction set computer (RISC) processor.
19. The method according to claim 1 , wherein said communicating is performed by one or more of a data dispatch engine or at least one reduced instruction set computer (RISC) processor.
20. A system for processing network information, the system comprising:
at least one processor within a single chip, said at least one processor enables classifying a header portion of a received packet based on connection context information within said received packet, wherein said at least one processor enables acquiring said connection context information from a memory external to said single chip;
said at least one processor enables updating said connection context information for said received packet based on said classifying; and
said at least one processor enables communicating at least a payload portion of said received packet to a destination, based on said updated connection context information.
21. The system according to claim 20 , wherein said at least one processor enables performing said classifying, updating and communicating asynchronously.
22. The system according to claim 20 , wherein said at least one processor enables parsing said header portion of said received packet.
23. The system according to claim 20 , wherein said at least one processor enables validating said header portion of said received packet.
24. The system according to claim 20 , wherein said at least one processor enables evaluating said connection context information of said received packet.
25. The system according to claim 20 , wherein said at least one processor enables evaluating said updated connection context information.
26. The system according to claim 20 , wherein said at least one processor enables executing said classifying during a first processing stage.
27. The system according to claim 20 , wherein said at least one processor enables executing said classifying at a first processing stage during a first period of time.
28. The system according to claim 27 , wherein said at least one processor enables executing said updating at a second processing stage during a second period of time, said second period of time independent of said first period of time.
29. The system according to claim 20 , wherein said connection context information is for an established connection.
30. The system according to claim 29 , wherein said memory comprises fast access memory.
31. The system according to claim 20 , wherein said at least one processor enables determining based on said connection context information, whether said received packet is marked for hardware acceleration processing.
32. The system according to claim 31 , wherein said at least one processor enables accelerating processing of said received packet, if said received packet is marked for said hardware acceleration processing.
33. The system according to claim 31 , wherein said at least one processor enables passing said received packet to a host processor for non-accelerated processing in software, if said received packet is not marked for said hardware acceleration processing.
34. The system according to claim 20 , wherein said at least one processor enables identifying whether a connection is to be removed based on one or more of said connection context information or said updated connection context information.
35. The system according to claim 34 , wherein said at least one processor enables instructing a synchronization module integrated within said chip to remove said connection, if said connection is to be removed.
36. The system according to claim 20 , wherein said at least one processor that enables said classifying comprises one or more of an analysis engine or at least one reduced instruction set computer (RISC) processor.
37. The system according to claim 20 , wherein said at least one processor that enables said updating comprises one or more of a context processing engine or at least one reduced instruction set computer (RISC) processor.
38. The system according to claim 20 , wherein said at least one processor that enables said communicating comprises one or more of a data dispatch engine or at least one reduced instruction set computer (RISC) processor.