Semiconductor processing system and program
View Patent ↗In a processing system of a linear tool in which plural carrying robots are arranged in carrying mechanical units to which processing modules are coupled and a processing target is delivered and received between the plural carrying robots, in the case where there are plural carrying routes on which the processing target is carried, the present invention provides a technique for determining the carrying route on which the highest throughput can be obtained. In the processing system of a linear tool, in the case where there are plural carrying routes on which the processing target is carried, the throughputs of the respective carrying routes are compared to each other, and the carrying route is determined by a unit for selecting the carrying route with the highest throughput.
1. A semiconductor processing system comprising:
plural processing modules configured to process a plurality of processing targets;
at least two carrying modules including carrying robots configured to deliver and receive the processing targets to/from the processing modules; and
an operation control unit configured to control operation of the processing modules and the carrying modules,
wherein each of the carrying modules is coupled to at least one of the plural processing modules, and the carrying modules are coupled to each other, and
the operation control unit is configured to generate a plurality of candidates of carrying routes for the plurality of processing targets using a device structure information of the semiconductor processing system, each of the plurality of candidates of carrying routes specifying whether one or both of the carrying modules will be used for one of the processing targets and which of the processing modules will be used for said one of the processing targets and including different routes constituted by different choices of the carrying module or carrying modules selected from the at least two carrying modules, and then determine specific carrying routes by calculating throughput of the each of the plurality of candidates of carrying routes for the plurality of processing targets based on the operation time of the carrying modules, processing time at the processing modules and operation time and processing time required for another one of the processing targets which will be processed.
2. The semiconductor processing system according to claim 1 ,
wherein the operation time of the carrying modules is set by the operation of each of the carrying robots.
3. The semiconductor processing system according to claim 1 ,
wherein the processing time at the processing modules is set by each of processing targets to be carried.
4. The semiconductor processing system according to claim 1 ,
wherein the operation control unit is configured to determine one of the specific carrying routes among the determined specific carrying routes with the highest throughput among the plurality of candidates.
5. The semiconductor processing system according to claim 1 ,
wherein the operation control unit comprises:
a processing module extracting unit configured to extract an available processing module among the plurality of the processing modules,
a carrying route candidate generating unit configured to generate a candidate for the carrying route on which the processing target is carried on the basis of information of the extracted available processing module, and
a throughput calculating unit configured to calculate the throughput of the generated carrying route.
6. The semiconductor processing system according to claim 5 ,
wherein the operation control unit is configured to generate destination candidate information used for carrying the processing target based on the information of the extracted available processing module and the carrying route candidate generating unit is configured to generate the carrying route candidate on which the processing target is carried using the generated destination candidate information and the device structure information that is preliminarily stored in a storing device.
7. The semiconductor processing system according to claim 6 ,
wherein the throughput calculating unit is configured to perform a simulation, for all the carrying route candidates, in which operations performed by the respective units on the basis of the destination candidate information, the carrying route candidate information, and the device structure information are laid out in time series, and to calculate the throughput of each carrying route candidate on the basis of the simulation result.
8. The semiconductor processing system according to claim 1 ,
wherein the carrying modules and the processing modules are kept at a vacuum state, one of the carrying modules is coupled to the load lock in which the pressure can be reduced or increased, and the processing targets are carried into the carrying modules through the load lock.
9. The semiconductor processing system according to claim 1 ,
wherein the one of the processing targets is processed in a series of the processes by using at least two of the plural processing modules.
10. A semiconductor processing method using plural processing modules configured for processing a plurality of processing targets, said method comprising:
delivering and receiving the processing target to/from the processing modules via at least two carrying modules which include carrying robots;
controlling operation of the processing modules and the carrying modules via an operation control unit, wherein each of the carrying modules is coupled to at least one of the plural processing modules, and,
generating a plurality of candidates of carrying routes, via the operation control unit for the plurality of processing targets using a device structure information of the semiconductor processing system, each of the plurality of candidates of carrying routes specifying whether one or both of the carrying modules will be used for one of the processing targets and which of the processing modules will be used for said one of the processing targets and including different routes constituted by different choices of the carrying module or carrying modules selected from the at least two carrying modules, and determining via the operation control unit, specific carrying routes by calculating throughput of an each of the plurality of candidates of the carrying routes for the plurality of processing targets based on the operation time of the carrying modules, processing time at the processing modules and operation time and processing time required for another one of the processing targets which will be processed.
11. The semiconductor processing method according to claim 10 ,
wherein the operation time of the carrying modules is set by the operation of each carrying robots.
12. The semiconductor processing method according to claim 10 ,
wherein the processing time at the processing modules is set by each of the processing targets to be carried.
13. The semiconductor processing method according to claim 10 , further comprising determining one of the specific carrying routes among the determined specific carrying route with the highest throughput among the plurality of candidates, via the operation control unit.
14. The semiconductor processing method according to claim 10 , further comprising:
extracting an available processing module among the plurality of the processing modules, via a processing module extracting unit;
generating a candidate for the carrying route on which the processing target is carried on the basis of information of the extracted available processing module, via a carrying route candidate generating unit; and
calculating the throughput of the generated carrying route via a throughput calculating module.
15. The semiconductor processing method according to claim 14 , further comprising:
generating, via the operation control unit, destination candidate information used for carrying the processing target based on the information of the extracted available processing module; and
generating, via the carrying route candidate generating unit, the carrying route candidate on which the processing target is carried using the generated destination candidate information and the device structure information that is preliminarily stored in a storing device.
16. The semiconductor processing method according to claim 15 , further comprising:
performing, via the throughput calculating unit, a simulation, for all the carrying route candidates, in which operations performed by the respective units on the basis of the destination candidate information, the carrying route candidate information, and the device structure information are laid out in time series: and
calculating the throughput of each carrying route candidate on the basis of the simulation result.
17. The semiconductor processing method according to claim 10 , further comprising:
keeping the carrying modules and the processing modules at a vacuum state;
coupling one of the carrying modules to the load lock in which the pressure can be reduced or increased; and
carrying the processing targets into the carrying modules through the load lock.
18. The semiconductor processing method according to claim 10 ,
wherein the one of the processing targets is processed in a series of the processes by using at least two of the plural processing modules.