Indium, carbon and halogen doping for PMOS transistors

1. An integrated circuit (IC), comprising:

a substrate having a semiconductor surface;

at least one PMOS transistor formed in said substrate, comprising:

a gate structure including a gate electrode on a gate dielectric formed over said semiconductor surface;

source/drain regions formed in said semiconductor surface on both sides of said gate structure, and

source/drain extension regions formed on both sides of said gate structure including co-doping comprising indium, carbon and a halogen each having minimum peak concentrations of 1×10 16 /cm 3 , wherein said source/drain regions are distanced from said gate structure further than said source/drain extension regions; and

wherein said at least one PMOS transistor includes at least one core PMOS transistor and at least one non-core PMOS transistor, wherein said indium, said halogen and said carbon are in said source/drain extension regions for said core PMOS transistor and at least one of said indium, said halogen and said carbon are not in said source/drain extension regions of said non-core PMOS transistor.

2. The IC of claim 1 , wherein said gate dielectric for said core PMOS transistor is at least 2 Å of equivalent oxide thickness (EOT) thinner as compared to said gate dielectric for said non-core PMOS transistor.

3. The IC of claim 1 , wherein said halogen comprises fluorine.

4. The IC of claim 1 , wherein said gate electrode comprises polysilicon.

5. The IC of claim 1 , wherein said gate electrode comprises a metal gate and said gate dielectric comprises a high-k dielectric.

6. The IC of claim 1 , further comprising halo regions formed on both sides of said gate structure including said at least one of said carbon and said halogen and said source/drain regions including at least one of one of said indium, carbon and said halogen.

7. A method of forming an integrated circuit (IC) including at least one core PMOS transistor and at least one non-core PMOS transistor, wherein said core PMOS transistor has a gate dielectric that is at least 2 Å of equivalent oxide thickness (EOT) thinner as compared to said non-core PMOS transistor, comprising:

performing PLDD implantation comprising co-implanting indium, carbon and a halogen and a boron comprising specie to establish source/drain extension regions in a substrate having a semiconductor surface on either side of a gate structure including a gate electrode comprising polysilicon on a gate dielectric formed on said semiconductor surface, wherein during said PLDD implantation said indium, said halogen and said carbon are implanted into said source/drain extension regions for said core PMOS transistor and at least one of said indium, said halogen and said carbon are not implanted into said source/drain extension regions of said non-core PMOS transistor;

performing source and drain implantation to establish source/drain regions, wherein said source/drain regions are distanced from said gate structure further than said source/drain extension regions, and

source/drain annealing after said performing source and drain implantation.

8. The method of claim 7 , wherein said source/drain annealing comprises at least one ultra high temperature (UHT) anneal, further comprising at least one UHT anneal after said co-implanting and before said performing source and drain implantation, said UHT anneals providing a peak anneal temperature of between 1050° C. and 1400° C. and an anneal time at said peak temperature ≦10 seconds.

9. The method of claim 7 , further comprising stress memorization technique (SMT) processing including deposition of at least one layer of tensile material after said performing source and drain implantation and before said source/drain anneal, wherein said layer of tensile material is on said core and said non-core PMOS transistors during said source/drain annealing.