Decoupling sampling clock and error clock in a data eye
In described embodiments, a transceiver includes an eye monitor, clock and data recovery, and adaptation modules. Data sampling clock phase and error clock phase determined from a data eye are decoupled in the transceiver during a sampling phase correction process. Decoupling these clock phases during the sampling phase correction process allows relative optimization of system equalization parameters without degradation of various adaptation algorithms. Such adaptation algorithms might be employed for received signal gain and equalization such as, for example, Decision Feedback Equalizer (DFE) adaptation. Deriving the data sampling clock and error clock phases from the same clock generation source and with independent clock control enables an iterative sampling phase correction process that allows for accelerated clock and data recovery (CDR) without disturbing the data eye shape.
1. An apparatus comprising:
a receiver comprising:
an eye monitor configured to generate a data eye from a data stream subject to equalization, the eye monitor including at least one error sampler, at least one transition sampler, and at least one data sampler;
a clock and data recovery (CDR) circuit configured to generate a transition clock for each transition sampler based on data transitions in the data eye, wherein the CDR shifts, in phase, the transition clock with a fixed phase offset to generate an error clock signal to each error sampler and, at an initial time, a data clock to each data sampler, and
an adaptation module configured to adaptively set parameters of equalization applied to the data stream based upon an output of the error sampler and an output of the data sampler,
wherein, at a subsequent time, the CDR decouples the error clock and the data clock to generate a relative optimum phase for the decoupled data clock for each data sampler.
2. The apparatus of claim 1 , wherein the equalization is applied to the data stream by an equalizer of the receiver, and wherein the equalizer is a decision feedback equalizer (DFE) of the receiver.
3. The apparatus of claim 2 , wherein a predefined range for the relative optimum phase for the data clock is based on a range of a bimodal distribution of a DFE-equalized data eye.
4. The apparatus of claim 1 , wherein, during an acquisition period, the adaptation module is further configured to obtain a CDR lock and an adaptation convergence, the acquisition period occurring between the initial time and the subsequent time.
5. The apparatus of claim 4 , wherein the adaptation module is further configured to adaptively set parameters of at least one of a filter and a gain applied to the data stream based upon an output of the error sampler.
6. The apparatus of claim 4 , wherein the data sampler comprises at least one latch including a first latch employed for data sampling at the initial time and a second latch employed at the subsequent time.
7. The apparatus of claim 1 , wherein:
the error sampler monitors a vertical position of the eye with respect to a center of the eye;
the data sampler samples the substantially center position of the eye, the center position corresponding to a data symbol,
wherein the outputs of at least one of the error sampler and the data sampler indicate a shift, in phase, of the center of the eye.
8. The apparatus of claim 7 , wherein the data sampler samples at the substantially center position of the eye to detect data symbols of the data stream.
9. The apparatus of claim 1 , wherein the CDR shifts, in phase, the transition clock with the fixed phase offset of substantially ½ UI (unit interval) ±N, N a phase and ½ UI ≧N≧0, to generate the data clock signal for each corresponding data sampler.
10. The apparatus of claim 1 , wherein the receiver is coupled to a transmitter and the adaptation module is in communication with the transmitter configured to provide the data stream,
wherein the transmitter, based on an indication of the adaptation module, adaptively sets parameters of each device of the transmitter in a signal path of the data stream, each device comprising at least one of a gain, a filter, and an equalizer.
11. The apparatus of claim 1 , wherein the apparatus is embodied in a Serial DeSerializer (SerDes) device.
12. A method comprising:
generating, with an eye monitor of a receiver, a data eye from a data stream subject to equalization, the eye
monitor including at least one error sampler, at least one transition sampler, and at least one data sampler;
generating, with a clock and data recovery (CDR) circuit of the receiver, a transition clock for each transition sampler based on data transitions in the data eye;
shifting, in phase, the transition clock with a fixed phase offset, thereby generating an error clock signal to each error sampler and, at an initial time, a data clock to each data sampler;
adaptively setting parameters of equalization applied to the data stream based upon an output of the error sampler and an output of the data sampler;
decoupling, by the CDR circuit, the error clock and the data clock; and
generating, at a subsequent time, a relative optimum phase for the decoupled data clock for each data sampler.
13. The method of claim 12 , further comprising, during an acquisition period, obtaining a CDR circuit lock and an adaptation convergence, the acquisition period occurring between the initial time and the subsequent time.
14. The method of claim 12 , comprising:
monitoring, with the error sampler, a vertical position of the eye with respect to at least one of a left of and a right of a center of the eye;
sampling, with the data sampler, the substantially center position of the eye, the center position corresponding to a data symbol,
indicating, by the outputs of at least one of the error sampler and the data sampler, a shift, in phase, of the center of the eye.
15. The method of claim 14 , wherein the data sampler samples the substantially center position of the eye to detect data symbols of the data stream.
16. The method of claim 12 , comprising shifting, in phase, by the CDR the transition clock with the fixed phase offset of substantially ½ UI (unit interval) ±N, N a phase and ½ UI ≧N≧0, to generate the data clock signal for each corresponding data sampler.
17. The method of claim 12 , wherein the receiver is coupled to a transmitter, further comprising adaptively setting parameters of each device of the transmitter in a signal path of the data stream, each device comprising at least one of a gain, a filter, and an equalizer.
18. The method of claim 12 , wherein the method is embodied as steps executed by a processor in a Serial DeSerializer (SerDes) device.
19. The method of claim 12 , further comprising initially aligning the error sampler and the data sampler before adaptively setting the parameters of the equalization.
20. A non-transitory machine-readable storage medium, having encoded thereon program code, wherein, when the program code is executed by a machine, the machine implements a method for adaptively setting equalization in a receiver, comprising the steps of:
generating, with an eye monitor of a receiver, a data eye from a data stream subject to equalization, the eye
monitor including at least one error sampler, at least one transition sampler, and at least one data sampler;
generating, with a clock and data recovery (CDR) circuit of the receiver, a transition clock for each transition sampler based on data transitions in the data eye;
shifting, in phase, the transition clock with a fixed phase offset, thereby generating an error clock signal to each error sampler and, at an initial time, a data clock to each data sampler;
adaptively setting parameters of equalization applied to the data stream based upon an output of the error sampler and an output of the data sampler;
decoupling, by the CDR circuit, the error clock and the data clock; and
generating, at a subsequent time, a relative optimum phase for the decoupled data clock for each data sampler.