IP Library › Granted Patent US 8,624,650
Granted Patent B2
US 8,624,650 · App. 12/972,623 · Granted Jan 7, 2014

Semiconductor device

Inventor: Masato Ishii (Isehara, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,624,650
App. No.
12/972,623
Granted
Jan 7, 2014
Kind
B2
Abstract

An object is to provide a low-power semiconductor device which does not require a latch circuit to hold data at the output of inverter circuits. In the semiconductor device, an input of a first inverter circuit is connected to an input terminal through a source and a drain of a first transistor. An input of a second inverter circuit is connected to an output of the first inverter circuit through a source and a drain of a second transistor. An output of the second inverter is connected to an output terminal. An inverted clock signal and a clock signal are input to gates of the first transistor and the second transistor, respectively. The first and the second transistor have extremely low off-current, which allows the output potential of the device to remain unchanged even when the input varies.

Claims (150)

1. A semiconductor device comprising:

a first transistor;

a second transistor;

a first inverter circuit comprising first inverter transistors; and

a second inverter circuit comprising second inverter transistors,

wherein one of a source and a drain of the first transistor is electrically connected to a first wiring;

wherein the other of the source and the drain of the first transistor is electrically connected to an input of the first inverter circuit;

wherein an output of the first inverter circuit is electrically connected to one of a source and a drain of the second transistor;

wherein the other of the source and the drain of the second transistor is electrically connected to an input of the second inverter circuit;

wherein an output of the second inverter circuit is electrically connected to a second wiring;

wherein each of the first transistor and the second transistor comprises a channel formation region in an oxide semiconductor layer; and

wherein at least one of the first inverter transistors and one of the second inverter transistors comprise a channel formation region in a material other than an oxide semiconductor material.

2. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a first inverter circuit comprising first inverter transistors; and

a second inverter circuit comprising second inverter transistors,

wherein the semiconductor device is configured to input a reset signal to a gate of the third transistor and a gate of the fourth transistor;

wherein one of a source and a drain of the first transistor is electrically connected to a first wiring;

wherein the other of the source and the drain of the first transistor is electrically connected to an input of the first inverter circuit;

wherein an output of the first inverter circuit is electrically connected to one of a source and a drain of the second transistor;

wherein the other of the source and the drain of the second transistor is electrically connected to an input of the second inverter circuit;

wherein an output of the second inverter circuit is electrically connected to a second wiring;

wherein one of a source and a drain of the third transistor is electrically connected to the input of the first inverter circuit;

wherein the other of the source and the drain of the third transistor is electrically connected to a low voltage supply line;

wherein one of a source and a drain of the fourth transistor is electrically connected to the input of the second inverter circuit;

wherein the other of the source and the drain of the fourth transistor is electrically connected to a high voltage supply line;

wherein each of the first transistor and the second transistor comprises a channel formation region in an oxide semiconductor layer; and

wherein at least one of the first inverter transistors and one of the second inverter transistors comprise a channel formation region in a material other than an oxide semiconductor material.

3. A semiconductor device comprising:

a first transistor;

a second transistor;

a fifth transistor;

a sixth transistor;

a first inverter circuit comprising first inverter transistors; and

a second inverter circuit comprising second inverter transistors,

wherein the semiconductor device is configured to input a set signal to a gate of the fifth transistor and a gate of the sixth transistor;

wherein one of a source and a drain of the first transistor is electrically connected to a first wiring;

wherein the other of the source and the drain of the first transistor is electrically connected to an input of the first inverter circuit;

wherein an output of the first inverter circuit is electrically connected to one of a source and a drain of the second transistor;

wherein the other of the source and the drain of the second transistor is electrically connected to an input of the second inverter circuit;

wherein an output of the second inverter circuit is electrically connected to a second wiring;

wherein one of a source and a drain of the fifth transistor is electrically connected to the input of the first inverter circuit;

wherein the other of the source and the drain of the fifth transistor is electrically connected to a high voltage supply line;

wherein one of a source and a drain of the sixth transistor is electrically connected to the input of the second inverter circuit;

wherein the other of the source and the drain of the sixth transistor is electrically connected to a low voltage supply line;

wherein each of the first transistor and the second transistor comprises a channel formation region in an oxide semiconductor layer; and

wherein at least one of the first inverter transistors and one of the second inverter transistors comprise a channel formation region in a material other than an oxide semiconductor material.

4. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor;

a first inverter circuit comprising first inverter transistors; and

a second inverter circuit comprising second inverter transistors,

wherein the semiconductor device is configured to input a reset signal to a gate of the third transistor and a gate of the fourth transistor;

wherein the semiconductor device is configured to input a set signal to a gate of the fifth transistor and a gate of the sixth transistor;

wherein one of a source and a drain of the first transistor is electrically connected to a first wiring;

wherein the other of the source and the drain of the first transistor is electrically connected to an input of the first inverter circuit;

wherein an output of the first inverter circuit is electrically connected to one of a source and a drain of the second transistor;

wherein the other of the source and the drain of the second transistor is electrically connected to an input of the second inverter circuit;

wherein an output of the second inverter circuit is electrically connected to a second wiring;

wherein one of a source and a drain of the third transistor is electrically connected to the input of the first inverter circuit;

wherein the other of the source and the drain of the third transistor is electrically connected to a low voltage supply line;

wherein one of a source and a drain of the fourth transistor is electrically connected to the input of the second inverter circuit;

wherein the other of the source and the drain of the fourth transistor is electrically connected to a high voltage supply line;

wherein one of a source and a drain of the fifth transistor is electrically connected to the input of the first inverter circuit;

wherein the other of the source and the drain of the fifth transistor is electrically connected to the high voltage supply line;

wherein one of a source and a drain of the sixth transistor is electrically connected to the input of the second inverter circuit;

wherein the other of the source and the drain of the sixth transistor is electrically connected to the low voltage supply line;

wherein each of the first transistor and the second transistor comprises a channel formation region in an oxide semiconductor layer; and

wherein at least one of the first inverter transistors and one of the second inverter transistors comprise a channel formation region in a material other than an oxide semiconductor material.

5. A semiconductor device comprising:

a first transistor;

a second transistor;

a first inverter circuit comprising first inverter transistors;

a second inverter circuit comprising second inverter transistors,

a first capacitor comprising a first pair of electrodes; and

a second capacitor comprising a second pair of electrodes,

wherein one of a source and a drain of the first transistor is electrically connected to a first wiring;

wherein the other of the source and the drain of the first transistor is electrically connected to an input of the first inverter circuit;

wherein an output of the first inverter circuit is electrically connected to one of a source and a drain of the second transistor;

wherein the other of the source and the drain of the second transistor is electrically connected to an input of the second inverter circuit;

wherein an output of the second inverter circuit is electrically connected to a second wiring;

wherein one electrode of the first capacitor is electrically connected to the input of the first inverter circuit;

wherein the other electrode of the first capacitor is electrically connected to a low voltage supply line;

wherein one electrode of the second capacitor is electrically connected to the input of the second inverter circuit;

wherein the other electrode of the second capacitor is electrically connected to the low voltage supply line;

wherein each of the first transistor and the second transistor comprises a channel formation region in an oxide semiconductor layer; and

wherein at least one of the first inverter transistors and one of the second inverter transistors comprise a channel formation region in a material other than an oxide semiconductor material.

6. The semiconductor device according to claim 1 , the semiconductor device being further configured to input an inverted clock signal to a gate of the first transistor and a clock signal to a gate of the second transistor.

7. The semiconductor device according to claim 2 , the semiconductor device being further configured to input an inverted clock signal to a gate of the first transistor and a clock signal to a gate of the second transistor.

8. The semiconductor device according to claim 3 , the semiconductor device being further configured to input an inverted clock signal to a gate of the first transistor and a clock signal to a gate of the second transistor.

9. The semiconductor device according to claim 4 , the semiconductor device being further configured to input an inverted clock signal to a gate of the first transistor and a clock signal to a gate of the second transistor.

10. The semiconductor device according to claim 5 , the semiconductor device being further configured to input an inverted clock signal to a gate of the first transistor and a clock signal to a gate of the second transistor.

11. The semiconductor device according to claim 2 , further comprising:

a first capacitor comprising a first pair of electrodes; and

a second capacitor comprising a second pair of electrodes,

wherein one electrode of the first capacitor is electrically connected to the input of the first inverter circuit;

wherein the other electrode of the first capacitor is electrically connected to the low voltage supply line;

wherein one electrode of the second capacitor is electrically connected to the input of the second inverter circuit; and

wherein the other electrode of the second capacitor is electrically connected to the low voltage supply line.

12. The semiconductor device according to claim 3 , further comprising:

a first capacitor comprising a first pair of electrodes; and

a second capacitor comprising a second pair of electrodes,

wherein one electrode of the first capacitor is electrically connected to the input of the first inverter circuit;

wherein the other electrode of the first capacitor is electrically connected to the low voltage supply line;

wherein one electrode of the second capacitor is electrically connected to the input of the second inverter circuit; and

wherein the other electrode of the second capacitor is electrically connected to the low voltage supply line.

13. The semiconductor device according to claim 4 , further comprising:

a first capacitor comprising a first pair of electrodes; and

a second capacitor comprising a second pair of electrodes,

wherein one electrode of the first capacitor is electrically connected to the input of the first inverter circuit;

wherein the other electrode of the first capacitor is electrically connected to the low voltage supply line;

wherein one electrode of the second capacitor is electrically connected to the input of the second inverter circuit; and

wherein the other electrode of the second capacitor is electrically connected to the low voltage supply line.

14. The semiconductor device according to claim 1 , wherein any of the first transistor and the second transistor includes an oxide semiconductor layer in which a carrier concentration is less than 1×10 14 /cm 3 .

15. The semiconductor device according to claim 2 , wherein any of the first transistor, the second transistor, the third transistor and the fourth transistor includes an oxide semiconductor layer in which a carrier concentration is less than 1×10 14 /cm 3 .

16. The semiconductor device according to claim 3 , wherein any of the first transistor, the second transistor, the fifth transistor and the sixth transistor includes an oxide semiconductor layer in which a carrier concentration is less than 1×10 14 /cm 3 .

17. The semiconductor device according to claim 4 , wherein any of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor includes an oxide semiconductor layer in which a carrier concentration is less than 1×10 14 /cm 3 .

18. The semiconductor device according to claim 5 , wherein any of the first transistor and the second transistor includes an oxide semiconductor layer in which a carrier concentration is less than 1×10 14 /cm 3 .

19. The semiconductor device according to claim 14 , wherein a band gap of the oxide semiconductor layer is 2 eV or more.

20. The semiconductor device according to claim 15 , wherein a band gap of the oxide semiconductor layer is 2 eV or more.

21. The semiconductor device according to claim 16 , wherein a band gap of the oxide semiconductor layer is 2 eV or more.

22. The semiconductor device according to claim 17 , wherein a band gap of the oxide semiconductor layer is 2 eV or more.

23. The semiconductor device according to claim 18 , wherein a band gap of the oxide semiconductor layer is 2 eV or more.

24. The semiconductor device according to claim 1 ,

wherein the first inverter circuit and the second inverter circuit each are a CMOS inverter circuit comprising at least a p-channel transistor with a channel formation region formed in silicon.

25. The semiconductor device according to claim 2 ,

wherein the first inverter circuit and the second inverter circuit each are a CMOS inverter circuit comprising at least a p-channel transistor with a channel formation region formed in silicon.

26. The semiconductor device according to claim 3 ,

wherein the first inverter circuit and the second inverter circuit each are a CMOS inverter circuit comprising at least a p-channel transistor with a channel formation region formed in silicon.

27. The semiconductor device according to claim 4 ,

wherein the first inverter circuit and the second inverter circuit each are a CMOS inverter circuit comprising at least a p-channel transistor with a channel formation region formed in silicon.

28. The semiconductor device according to claim 5 ,

wherein the first inverter circuit and the second inverter circuit each are a CMOS inverter circuit comprising at least a p-channel transistor with a channel formation region formed in silicon.

29. The semiconductor device according to claim 1 , wherein the semiconductor device is a flip-flop.

30. The semiconductor device according to claim 2 , wherein the semiconductor device is a flip-flop.

31. The semiconductor device according to claim 3 , wherein the semiconductor device is a flip-flop.

32. The semiconductor device according to claim 4 , wherein the semiconductor device is a flip-flop.

33. The semiconductor device according to claim 5 , wherein the semiconductor device is a flip-flop.

34. An electronic appliance including the semiconductor device according to claim 1 .

35. An electronic appliance including the semiconductor device according to claim 2 .

36. An electronic appliance including the semiconductor device according to claim 3 .

37. An electronic appliance including the semiconductor device according to claim 4 .

38. An electronic appliance including the semiconductor device according to claim 5 .

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 20, 2010
From: ISHII, MASATO
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 025524/0436 →
Priority Claims (1)
JP 2009-291587 · Dec 23, 2009 · national
Continuity (1)
Related Publication 20110148497A1 · Jun 23, 2011