ESD protection circuit with EOS immunity

1. An ESD protection circuit comprising:

a first connection circuit coupled between a pad and a first clamp node;

a first EOS control circuit coupled between the first clamp node and an I/O clamp node; and

an ESD clamp coupled between the I/O clamp node and a second power node; the ESD clamp working in a triggered conduction mode and a reverse conduction mode; wherein when the ESD clamp detects ESD, the ESD clamp works in the triggered conduction mode conducting the I/O clamp node to the second power node; when a voltage of the I/O clamp node is greater than a first characteristic voltage, the ESD clamp works in the reverse conduction mode conducting the I/O clamp node to the second power node;

wherein when the pad receives EOS, the first EOS control circuit provides a first cross voltage between the first clamp node and the I/O clamp node such that the voltage of the I/O clamp node is less than the first characteristic voltage to prevent the ESD clamp from conducting between the I/O clamp node and the second power node, and

wherein the ESD protection circuit is built within a single power domain between a first power node and the second power node, and the first clamp node is detached from the first power node.

2. The ESD protection circuit of claim 1 further comprising:

a second EOS control circuit coupled between the first clamp node and the I/O clamp node;

wherein the first connection circuit works in a forward conduction mode and a reverse conduction mode; when the first connection circuit works in the forward conduction mode, the first connection circuit conducts the pad to the first clamp node; when a voltage difference between the first clamp node and the pad is greater than a second characteristic voltage, the first connection circuit works in the reverse conduction mode conducting the first clamp node to the pad; and

wherein when the second power node receives EOS, the second EOS control circuit provides a second cross voltage between the I/O clamp node and the first clamp node such that the voltage difference between the first clamp node and the pad is less than the second characteristic voltage to keep the first connection circuit from conducting.

3. The ESD protection circuit of claim 1 , wherein the first EOS control circuit comprises at least a p-n junction element for providing a p-n junction between the first clamp node and the I/O clamp node.

4. The ESD protection circuit of claim 3 , wherein the p-n junction element is a diode.

5. The ESD protection circuit of claim 2 , wherein the second EOS control circuit comprises at least a p-n junction element for providing a p-n junction between the I/O clamp node and the first clamp node.

6. The ESD protection circuit of claim 2 , wherein the first connection circuit provides a p-n junction between the pad and the first clamp node, and the second characteristic voltage is a breakdown voltage of the p-n junction.

7. The ESD protection circuit of claim 1 , wherein the first connection circuit provides a p-n junction between the pad and the first clamp node.

8. The ESD protection circuit of claim 1 , wherein the first connection circuit comprises a p-channel metal-oxide-semiconductor field effect transistor with a gate and a source coupled to the first clamp node and a drain coupled to the pad.

9. The ESD protection circuit of claim 1 , wherein the first connection circuit comprises a p-n-p bipolar junction transistor with an emitter and a base coupled to the first clamp node and a collector coupled to the pad.

10. The ESD protection circuit of claim 1 further comprising:

a second connection circuit coupled between the pad and the second power node; when ESD occurs between the second power node and the pad, the second connection circuit conducts the second power node to the pad.

11. The ESD protection circuit of claim 1 further comprising:

a third connection circuit coupled between a the first power node and the I/O clamp node, wherein the first clamp node is coupled to the I/O clamp node bypassing the first power node.

12. The ESD protection circuit of claim 11 further comprising:

a power clamp coupled between the first power node and the second power node.

13. The ESD protection circuit of claim 1 , wherein the ESD clamp comprises:

an ESD detector coupled between the I/O clamp node and the second power node detecting ESD occurrence and providing a trigger signal in response to ESD detection; and

a discharge circuit coupled between the ESD detector, the I/O clamp node and the second power node; wherein when ESD detection reflects ESD occurrence, the discharge circuit conducts the I/O clamp node to the second power node as the ESD clamp works in the triggered conduction mode.

14. The ESD protection circuit of claim 13 , wherein when ESD detection does not reflect ESD occurrence, if a voltage difference between the I/O clamp node and the second power node is greater than the first characteristic voltage, the discharge circuit conducts the I/O clamp node to the second power node as the ESD clamp works in the reverse conduction mode.

15. The ESD protection circuit of claim 13 wherein the first characteristic voltage is a breakdown voltage of the discharge circuit.

16. The ESD protection circuit of claim 1 further comprising:

a current limiter coupled between the pad and an internal circuit; and

a voltage divider coupled between the current limiter and the internal circuit; wherein when the pad receives EOS, the voltage divider provides a third cross voltage, which is less than a voltage of EOS, to the internal circuit.

17. The ESD protection circuit of claim 16 wherein the voltage divider comprises:

a resistor, and

an n-channel metal-oxide-semiconductor field effect transistor with a gate and a source coupled to the second power node and a drain coupled to the resistor.