Techniques for providing a semiconductor memory device having hierarchical bit lines
View Patent ↗Techniques for providing a semiconductor memory device having hierarchical bit lines are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells and a plurality of local bit lines coupled directly to the plurality of memory cells. The semiconductor memory device may also include a multiplexer coupled to the plurality of local bit lines and a global bit line coupled to the multiplexer.
1. A semiconductor memory device comprising:
a plurality of memory cells;
a plurality of local bit lines coupled directly to the plurality of memory cells;
a multiplexer coupled to the plurality of local bit lines, wherein the multiplexer comprises a plurality of hold transistors each configured to apply a holding signal to a respective memory cell during a hold operation; and
a global bit line coupled to the multiplexer.
2. The semiconductor memory device according to claim 1 , wherein four local bit lines are coupled directly to the multiplexer.
3. The semiconductor memory device according to claim 1 , wherein the multiplexer is coupled to a global hold line.
4. The semiconductor memory device according to claim 1 , wherein the multiplexer is coupled to a global mask line.
5. The semiconductor memory device according to claim 1 , wherein the multiplexer further comprises a plurality of selection transistors.
6. The semiconductor memory device according to claim 5 , wherein the plurality of selection transistors are coupled to the plurality of memory cells via the plurality of local bit lines.
7. The semiconductor memory device according to claim 5 , wherein the plurality of selection transistors are coupled to the global bit line.
8. The semiconductor memory device according to claim 5 , wherein each of the plurality of selection transistors is coupled to a respective one of the plurality of memory cells.
9. The semiconductor memory device according to claim 1 , wherein the plurality of hold transistors are coupled to the plurality of local bit lines.
10. The semiconductor memory device according to claim 9 , wherein each of the plurality of hold transistors are coupled to a respective one of the plurality of local bit lines.
11. The semiconductor memory device according to claim 1 , wherein the plurality of hold transistors are coupled to a global hold line.
12. The semiconductor memory device according to claim 1 , wherein the multiplexer further comprises a plurality of mask transistors.
13. The semiconductor memory device according to claim 12 , wherein each of the plurality of mask transistors is coupled to a respective one of the plurality of local bit lines.
14. The semiconductor memory device according to claim 12 , wherein the plurality of mask transistors are coupled to a global mask line.
15. The semiconductor memory device according to claim 1 , wherein the multiplexer further comprises a plurality of selection transistors and a plurality of mask transistors.
16. The semiconductor memory device according to claim 15 , wherein each of the plurality of selection transistors, each of the plurality of mask transistors, and each of the plurality of hold transistors is directly coupled to a respective one of the plurality of local bit lines.
17. The semiconductor memory device according to claim 15 , wherein the plurality of mask transistors are coupled to a global mask line and the plurality of hold transistors are coupled to a global hold line.
18. The semiconductor memory device according to claim 17 , wherein the global mask line is configured between adjacent global bit lines.
19. The semiconductor memory device according to claim 17 , wherein the global hold line is configured between adjacent global bit lines.