IP Library Granted Patent US 8,466,403
Granted Patent B2
US 8,466,403 · App. 12/975,088 · Granted Jun 18, 2013

Solid-state image pickup apparatus and image pickup system

Inventors: Nobuyuki Endo (Fujisawa, JP); Tetsuya Itano (Sagamihara, JP); Kazuo Yamazaki (Ebina, JP); Kyouhei Watanabe (Yokohama, JP); Takeshi Ichikawa (Hachioji, JP)
Assignee: Canon Kabushiki Kaisha
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Quick Facts
Patent No.
US 8,466,403
App. No.
12/975,088
Granted
Jun 18, 2013
Kind
B2
Abstract

An apparatus according to the present invention in which a first substrate including a photoelectric conversion element and a gate electrode of a transistor, and a second substrate including a peripheral circuit portion are placed upon each other. The first substrate does not include a high-melting-metal compound layer, and the second substrate includes a high-melting-metal compound layer.

Claims (39)

1. An apparatus in which a first substrate and a second substrate are placed upon each other, the first substrate being where a photoelectric conversion element and a gate electrode of a transfer transistor for transferring an electric charge from the photoelectric conversion element are disposed, the second substrate being where a peripheral circuit portion for reading out a signal based on the electric charge generated at the photoelectric conversion element is disposed,

wherein the second substrate is provided with a high-melting-metal compound layer, and

wherein the first substrate is not provided with a high-melting-metal compound layer.

2. The apparatus according to claim 1 , wherein an upper portion of the first substrate is provided with a wiring layer including an aluminum wire or a copper wire, and

wherein an upper portion of the second substrate is provided with a wiring layer including an aluminum wire or a copper wire.

3. The apparatus according to claim 1 , comprising a diffusion prevention film disposed between the first substrate and the second substrate.

4. The apparatus according to claim 1 , wherein a principal surface of the first substrate where the gate electrode is disposed and a principal surface of the second substrate where a transistor of the peripheral circuit portion is disposed are placed upon each other.

5. The apparatus according to claim 4 further comprising a diffusion prevention film disposed between the first substrate and the second substrate.

6. The apparatus according to claim 5 , further comprising a wiring layer and an interlayer insulating film disposed above the first substrate,

wherein the diffusion prevention film is the interlayer insulating film disposed at the first substrate.

7. The apparatus according to claim 5 further comprising a wiring layer and an interlayer insulating film disposed above the second substrate,

wherein the diffusion prevention film is the interlayer insulating film disposed at the second substrate.

8. The apparatus according to claim 5 , wherein the diffusion prevention film is disposed so as to contact the high-melting-metal compound layer of a transistor including the high-melting-metal compound layer disposed at the second substrate.

9. The apparatus according to claim 5 , wherein at least an upper portion of the first substrate or an upper portion of the second substrate is provided with a wiring layer including copper wire,

wherein an upper portion of the wiring layer including the copper wire is provided with a diffusion prevention film, and

wherein the diffusion prevention film which prevents the diffusion of copper functions as the diffusion prevention film which prevents the diffusion of the high-melting metal.

10. The apparatus according to claim 1 , wherein a principal surface of the first substrate where the gate electrode is disposed and a surface opposite to a principal surface of the second substrate where a transistor is formed in the peripheral circuit portion are placed upon each other.

11. The apparatus according to claim 10 further comprising a diffusion prevention film disposed between the first substrate and the second substrate.

12. The apparatus according to claim 11 further comprising a wiring layer and an interlayer insulating film disposed so as to contact the wiring layer disposed above the first substrate,

wherein the diffusion prevention film is the interlayer insulating film disposed at the first substrate.

13. The apparatus according to claim 11 , wherein the diffusion prevention film is disposed so as to contact a back surface of the second substrate.

14. The apparatus according to claim 11 further comprising:

a wiring layer including a copper wire disposed above the first substrate; and

a diffusion prevention film provided on the wiring layer including the copper wire,

wherein the diffusion prevention film which prevents the diffusion of copper functions as the diffusion prevention film which prevents the diffusion of the high-melting metal.

15. The apparatus according to claim 1 , wherein the first substrate is provided with a floating diffusion region where the electric charge is transferred from the photoelectric conversion element by the gate electrode of the transfer transistor, and

wherein the second substrate is provided with an amplification transistor including a gate electrode to which a signal based on an electrical potential of the floating diffusion region is input, and a reset transistor for setting the gate electrode of the amplification transistor to a reset electrical potential, and wherein an upper portion of the second substrate is provided with a signal line where a signal based on the gate electrode of the amplification transistor is output.

16. The apparatus according to claim 1 , wherein the first substrate is provided with a floating diffusion region where the electric charge is transferred from the photoelectric conversion element by the gate electrode of the transfer transistor, an amplification transistor including a gate electrode to which a signal based on an electrical potential of the floating diffusion region is input, and a reset transistor for setting the gate electrode of the amplification transistor to a reset electrical potential, and

wherein an upper portion of the second substrate is provided with a signal line where a signal based on the gate electrode of the amplification transistor is output.

17. A system comprising:

the apparatus according to claim 1 ; and

a signal processing section that processes a signal output from the apparatus.

18. The apparatus according to claim 10 , wherein the first substrate is provided with a floating diffusion region where the electric charge is transferred from the photoelectric conversion element by the gate electrode of the transfer transistor, and

wherein the second substrate is provided with an amplification transistor including a gate electrode to which a signal based on an electrical potential of the floating diffusion region is input, and a reset transistor for setting the gate electrode of the amplification transistor to a reset electrical potential, and wherein an upper portion of the second substrate is provided with a signal line where a signal based on the gate electrode of the amplification transistor is output.

19. The apparatus according to claim 1 , wherein the first substrate is provided with a floating diffusion region where the electric charge is transferred from the photoelectric conversion element by the gate electrode of the transfer transistor, an amplification transistor including a gate electrode to which a signal based on an electrical potential of the floating diffusion region is input, and a reset transistor for setting the gate electrode of the amplification transistor to a reset electrical potential, and

wherein an upper portion of the second substrate is provided with a signal line where a signal based on the gate electrode of the amplification transistor is output.

20. A system comprising:

the apparatus according to claim 2 ; and

a signal processing section that processes a signal output from the apparatus.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2011
From: ENDO, NOBUYUKI; ITANO, TETSUYA; YAMAZAKI, KAZUO; WATANABE, KYOUHEI; ICHIKAWA, TAKESHI
To: CANON KABUSHIKI KAISHA
Reel/Frame 026035/0607 →
Priority Claims (1)
WO PCT/JP2009/071703 · Dec 26, 2009 · international
Continuity (1)
Related Publication 20110155893A1 · Jun 30, 2011