Substrates having voltage switchable dielectric materials
Various aspects provide for incorporating a VSDM into a substrate to create an ESD-protected substrate. In some cases, a VSDM is incorporated in a manner that results in the ESD-protected substrate meeting one or more specifications (e.g., thickness, planarity, and the like) for various subsequent processes or applications. Various aspects provide for designing a substrate (e.g., a PCB) incorporating a VSDM, and adjusting one or more aspects of the substrate to design a balanced, ESD-protected substrate. Certain embodiments include molding a substrate having a VSDM layer into a first shape.
1. A printed circuit board comprising:
a prepreg layer having a first surface and a second surface;
a voltage switchable dielectric material layer on the first surface of the prepreg layer, the prepreg layer and the voltage switchable dielectric material layer defining a first region subject to warpage when subjected to a particular process comprising at least one of curing, etching, and solder re-flowing subjected to the printed circuit board;
a first balance material layer on the second surface of the prepreg layer, the first balance material layer fully disposed on a same side of a centerline of the printed circuit board as the voltage switchable dielectric material layer, the centerline representing an approximate center of the printed circuit board when viewed parallel to the plane of the printed circuit board; and
a second balance material layer fully disposed on an opposite side of the centerline of the printed circuit board, wherein the first balance material layer is a first distance from the centerline and the second balance material layer is a second distance from the centerline, the second distance greater than the first distance, the prepreg layer and the first balance material layer defining a second region to counteract the warpage of the first region, the warpage is induced and associated with the voltage switchable dielectric material layer, such that the prepreg layer, the voltage switchable dielectric material layer and the first balance material layer define a multi-layer stack which is flat when subjected to the particular process.
2. The printed circuit board of claim 1 , wherein at least one of the first and second balance material layers has a thickness dependent upon a thickness of the voltage switchable dielectric material layer.
3. The printed circuit board of claim 1 , wherein a thicknesses of at least one of the first and second balance material layers and the voltage switchable dielectric material layer are independent of a thickness of the prepreg layer.
4. The printed circuit board of claim 1 , wherein the voltage switchable dielectric material layer has different properties than that of the first balance material layer.
5. The printed circuit board of claim 4 , wherein the different properties of the voltage switchable dielectric material layer and the first balance material layer include at least one of a different coefficient of thermal expansion, thickness, and elastic modulus.
6. The printed circuit board of claim 1 wherein:
the prepreg layer has a thickness of about 125 micrometers;
the voltage switchable dielectric material layer has a thickness of about 25 micrometers; and
the first balance material layer has a thickness of about 45 micrometers.
7. The printed circuit board of claim 1 , wherein:
the prepreg layer has a thickness of about 55 micrometers;
the voltage switchable dielectric material layer has a thickness of about 25 micrometers; and
the first balance material layer has a thickness of about 45 micrometers.
8. The printed circuit board of claim 1 , wherein the prepreg layer has thickness of less than about 300 micrometers.
9. The printed circuit board of claim 1 , wherein:
the prepreg layer has a thickness of about 25 micrometers;
the voltage switchable dielectric material layer has a thickness of about 25 micrometers; and
the first balance material layer has a thickness of about 35 micrometers.
10. The printed circuit board of claim 1 , wherein one or more layers are disposed between the second balance material layer and the centerline.
11. The printed circuit board of claim 10 , wherein the one or more layers comprises at least one additional prepreg layer.
12. The printed circuit board of claim 1 , wherein the first balance material layer is adjacent to the centerline.
13. The printed circuit board of claim 1 , wherein the first and second balance material layers are non-conductive.
14. The printed circuit board of claim 1 , wherein the centerline represents an approximate midpoint of a thickness of the printed circuit board.