Liquid crystal display device and method of driving the same
A liquid crystal display device includes a plurality of pixels at intersections of a plurality of row lines and a plurality of column lines, wherein each pixel includes a switching transistor, and pixel and common electrodes that induce an in-plane electric field; a plurality of gate lines each connected to the pixels on each row line; a plurality of data lines each connected to the pixels on each column line; and a plurality of common lines each connected to the common electrodes of the pixels alternately located on neighboring two row lines per one column line.
1. A liquid crystal display device, comprising:
a plurality of pixels at intersections of a plurality of row lines and a plurality of column lines, wherein each pixel includes a switching transistor, and pixel and common electrodes that induce an in-plane electric field;
a plurality of gate lines each connected to the pixels on each row line;
a plurality of data lines each connected to the pixels on each column line; and
a plurality of common lines each of which is alternately connected to the common electrodes of the pixels on a first row line of neighboring two row lines, and to the common electrode of the pixels on a second row line of the neighboring two row lines,
wherein the common line includes a first sub-line connected to the common electrodes of the pixels on the first row line among the neighboring two row lines, and a second sub-line connected to the common electrodes of the pixels on the second row line among the neighboring two row lines.
2. The device according to claim 1 , wherein the gate line is between the first and second sub-lines.
3. The device according to claim 2 , wherein the common line comprises a branch-off portion, where the common line branches off into the first and second sub-lines.
4. The device according to claim 1 , wherein a common voltage supplied to one of the common lines is in synchronization with a corresponding gate voltage supplied to the gate line connected to the pixels.
5. The device according to claim 1 , wherein a common voltage supplied to one of the common lines is in synchronization with a corresponding gate voltage supplied to the gate line connected to the pixels on the first row line among the neighboring two row lines.
6. The device according to claim 1 , wherein a top common line of the plurality of common lines is connected to the common electrodes of the pixels connected to the top common line and on a top row line of the plurality of gate lines.
7. The device according to claim 1 , wherein a bottom common line of the plurality of common lines is connected to the common electrodes of the pixels connected to the bottom common line and on a bottom row line of the plurality of gate lines.
8. A method of driving a liquid crystal display device, the liquid crystal display device including a plurality of pixels at intersections of a plurality of row lines and a plurality of column lines, wherein each pixel includes a switching transistor, and pixel and common electrodes that induce an in-plane electric field, the method comprising steps of:
sequentially supplying a plurality of gate voltages to a plurality of gate lines that are each connected to the pixels on each row line;
supplying a plurality of data voltages to a plurality of data lines, that are each connected to the pixels on each column line, in synchronization with each corresponding gate voltage; and
sequentially supplying a plurality of common voltages to a plurality of common lines each of which is alternately connected to the common electrodes of the pixels on a first row line of neighboring two row lines, and to the common electrode of the pixels on a second row line of the neighboring two row lines, with polarity inversion,
wherein the common line includes a first sub-line connected to the common electrodes of the pixels on the first row line among the neighboring two row lines, and a second sub-line connected to the common electrodes of the pixels on the second row line among the neighboring two row lines.
9. The method according to claim 8 , wherein the common voltage of the common line is in synchronization with the gate voltage of the gate line connected to the pixels on the first row line among the neighboring two row lines.
10. The method according to claim 8 , wherein the gate line is between the first and second sub-lines.
11. The method according to claim 10 , wherein the common line comprises a branch-off portion, where the common line branches off into the first and second sub-lines.
12. The method according to claim 8 , wherein a common voltage supplied to one of the common lines is in synchronization with a corresponding gate voltage supplied to the gate line connected to the pixels.
13. The method according to claim 8 , wherein a common voltage supplied to one of the common lines is in synchronization with a corresponding gate voltage supplied to the gate line connected to the pixels on the first row line among the neighboring two row lines.
14. The method according to claim 8 , wherein a top common line of the plurality of common lines is connected to the common electrodes of the pixels connected to the top common line and on a top row line of the plurality of gate lines.
15. The method according to claim 8 , wherein a bottom common line of the plurality of common lines is connected to the common electrodes of the pixels connected to the bottom common line and on a bottom row line of the plurality of gate lines.