IP Library Granted Patent US 8,617,987
Granted Patent B2
US 8,617,987 · App. 12/982,697 · Granted Dec 31, 2013

Through hole via filling using electroless plating

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Quick Facts
Patent No.
US 8,617,987
App. No.
12/982,697
Granted
Dec 31, 2013
Kind
B2
Abstract

An embedded wafer level ball grid array (eWLB) is formed by embedding a semiconductor die in a molding compound. A trench is formed in the molding compound with a laser drill. A first layer of copper is deposited on the sidewall of the trench by physical vapor deposition. A second layer of copper is then formed on the first layer of copper by an electroless process. A third layer of copper is then formed on the second layer by electroplating.

Claims (23)

1. A method comprising:

forming an aperture in a substrate;

attaching an integrated circuit die to the substrate;

depositing a first layer of conductive material in the aperture and on a contact pad of the integrated circuit die by physical vapor deposition;

depositing a second layer of conductive material in the aperture and on the contact pad by electroless plating; and

depositing a third layer of conductive material in the aperture and on the contact pad by electroplating.

2. The method of claim 1 , further comprising depositing a barrier layer in the aperture prior to depositing the first layer of conductive material.

3. The method of claim 2 wherein the barrier layer is formed of a material selected from a group consisting of TiW, Ti, Cr, TiN, and TaN.

4. The method of claim 1 , further comprising filling the aperture with a dielectric material.

5. The method of claim 1 wherein the first layer of conductive material is copper.

6. The method of claim 1 wherein the second and third layers of conductive material are copper.

7. A method comprising:

attaching a first integrated circuit die to a substrate;

forming an aperture in a substrate;

forming a first layer of copper in the aperture and on a contact pad of the integrated circuit die;

forming a second layer of copper in the aperture and on the contact pad;

forming a third layer of copper in the aperture and on the contact pad;

placing a first solder ball on over a first surface of the substrate; and

electrically connecting the solder ball to the first layer of copper.

8. The method of claim 7 comprising:

placing a second integrated circuit over a second surface of the substrate; and

electrically connecting a contact pad of the second integrated circuit to the first layer of copper.

9. The method of claim 7 wherein a second solder ball is between the second integrated circuit and the second surface of the substrate, the second solder ball being electrically connected to the contact pad of the second integrated circuit.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2024
From: STMICROELECTRONICS PTE LTD
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 068433/0985 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 19, 2011
From: GAN, KAH WEE; JIN, YONGGANG; LIU, YUN; HUANG, YAOHUANG
To: STMICROELECTRONICS PTE LTD.
Reel/Frame 026151/0894 →