High voltage-resistant semiconductor device and method of manufacturing high voltage-resistant semiconductor device
View Patent ↗High voltage-resistant semiconductor devices adapted to control threshold voltage by utilizing threshold voltage variation caused by plasma damage resulting from the formation of multilayer wiring, and a manufacturing method thereof. Exemplary high voltage-resistant semiconductor devices include a plurality of MOS transistors having gate insulating films not less than about 350 Å in thickness on a silicon substrate, and the MOS transistors have different area ratios between gate electrode-gate insulating film contact areas and total opening areas of contacts formed on the gate electrodes.
1. A method for manufacturing a high voltage-resistant semiconductor device, the method comprising:
preparing a silicon substrate having a plurality of transistor forming regions;
forming a plurality of transistors by:
forming channel regions in a superficial layer region on the transistor forming regions of the semiconductor substrate,
forming gate insulating films having film thicknesses greater than about 350 Å on the channel regions,
forming gate electrodes on the gate insulating films, and
forming source regions and drain regions on both sides of the channel regions;
providing contacts on the gate electrodes of the plurality of transistors; and
providing multilayer wiring on the contacts;
wherein an area ratio, Sc/Sg, associated with at least one of the plurality of transistors differs from area ratios, Sc/Sg, associated with at least another of the plurality of transistors, where Sc is a total opening area of the contacts provided on the gate electrodes of the respective transistor when viewed from a gate electrode side of the respective transistor, and where Sg is a contact area between the gate electrodes and the gate insulating film of the respective transistor.
2. The method of claim 1 , wherein a difference between the area ratio, Sc/Sg, associated with at least one of the plurality of transistors is greater than 10% of an average of the area ratios, Sc/Sg, associated with all of the plurality of transistors.
3. The method of claim 1 , wherein the act of providing contacts includes forming a contact hole by plasma etching using an etching gas including at least one of CF 4 , C 4 F 8 , C 5 F 8 , and CHF 3 .
4. The method of claim 1 , wherein the act of providing contacts includes covering at least one of the plurality of transistors with an intermediate film, applying a mask, forming a contact hole, removing the mask, and filling the contact hole with a contact material.
5. The method of claim 1 , wherein the act of providing multilayer wiring includes forming a first wiring layer over at least one of the contacts, covering the first wiring layer with a first interlayer film, forming a first via in the first interlayer film, and forming a second wiring layer over the first via.
6. The method of claim 1 , further comprising the acts of
forming a digital circuit in electrical communication with the plurality of transistors in a first of the plurality of transistor forming regions; and,
forming an analog circuit in electrical communication with the plurality of transistors in a second of the plurality of transistor forming regions.
7. The method of claim 1 , wherein the act of forming gate electrodes on the gate insulating films includes providing the gate electrodes with the same width.
8. A method for manufacturing a high voltage-resistant semiconductor device, the method comprising:
forming a plurality of metal-oxide-semiconductor transistors on a silicon substrate, each of the plurality of transistors fabricated by:
(a) forming a gate insulating film having a thickness greater than about 350 Å,
(b) forming a gate electrode over the gate insulating film, and
(c) forming a contact over the gate electrode;
wherein a respective area ratio, Sc/Sg, is associated with each of the plurality of transistors, where Sc is a total opening area of the at least one contact formed on the at least one gate electrode of the respective transistor when viewed from a gate electrode side of the respective transistor, and where Sg is a contact area between the at least one gate electrode and the gate insulating film of the respective transistor; and
wherein at least two of the plurality of transistors are formed with different area ratios.
9. The method of claim 8 , wherein a difference between the area ratio, Sc/Sg, associated with at least one of the plurality of transistors is greater than 10% of an average of the area ratios, Sc/Sg, associated with all of the plurality of transistors.
10. The method of claim 8 , wherein the act of forming the contact over the gate electrode includes forming at least one contact to have a shape substantially similar to at least one of a source contact formed on a source region and a drain contact formed on a drain region.
11. The method of claim 8 , wherein at least one of the contacts has a cross-sectional area of less than about 0.16 μm 2 .
12. The method of claim 8 , wherein the gate insulating film includes at least one of SiO 2 and an oxynitride.
13. The method of claim 8 , wherein at least one of the gate electrodes includes at least one of poly-Si, WSiX, and W.
14. The method of claim 8 , wherein at least one of the contacts includes at least one of poly-Si, Al, W, and Cu.
15. The method of claim 8 , further comprising the acts of:
forming a wire touching the contact, the wire fabricated using at least one of an Al—Cu alloy, Al—Cu—Si, and Cu; and
forming an intermediate film at partially around the wire, the intermediate film including SiO 2 .
16. The method of claim 8 , further comprising the acts of:
forming a digital circuit in electrical communication with a first of the at least two of the plurality of metal-oxide-semiconductor transistors; and,
forming an analog circuit in electrical communication with a second of the at least two of the plurality of metal-oxide-semiconductor transistors.
17. The method of claim 8 , wherein the gate electrodes formed over the gate insulting films have the same width.
18. The method of claim 8 , further comprising the act of providing multilayer wiring on the contact.
19. A method of manufacturing a high voltage-resistant semiconductor device comprising:
forming plurality of metal-oxide-semiconductor transistors on a silicon substrate, each of the plurality of transistors fabricated by:
(a) forming a gate insulating film having a thickness greater than a thickness of the gate insulating film in which a threshold voltage variation amount substantially increases with respect to lower thicknesses,
(b) forming a gate electrode over the gate insulating film, and
(c) forming a contact over the gate electrode;
wherein a respective area ratio, Sc/Sg, is associated with each of the plurality of transistors, where Sc is a total opening area of the at least one contact formed on the at least one gate electrode of the respective transistor when viewed from a gate electrode side of the respective transistor, and where Sg is a contact area between the at least one gate electrode and the gate insulating film of the respective transistor; and
wherein at least two of the plurality of transistors are formed with different area ratios.
20. The method of claim 19 , wherein a difference between the area ratio, Sc/Sg, associated with at least one of the plurality of transistors is greater than 10% of an average of the area ratios; Sc/Sg, associated with all of the plurality of transistors.
21. The method of claim 19 , wherein the act of forming the contact over the gate electrode includes forming at least one of the contacts to have a shape substantially similar to at least one of a source contact formed on a source region and a drain contact formed on a drain region.
22. The method of claim 19 , wherein at least one of the contacts has a cross-sectional area of less than about 0.16 μm 2 .
23. The method of claim 19 , wherein at least one of the contacts includes at least one of poly-Si, Al, W, and Cu.
24. The method of claim 19 , further comprising the acts of:
forming a wire touching the contact, the wire fabricated using at least one of an Al—Cu alloy, Al—Cu—Si, and Cu; and
forming an intermediate film at partially around the wire, the intermediate film including SiO 2 .
25. The method of claim 19 , wherein the thickness of the gate insulating film is greater than about 350 Å.
26. The method of claim 19 , further comprising the acts of:
forming a digital circuit in electrical communication with a first of the at least two of the plurality of metal-oxide-semiconductor transistors; and,
forming an analog circuit in electrical communication with a second of the at least two of the plurality of metal-oxide-semiconductor transistors.
27. The method of claim 19 , further comprising the act of providing multilayer wiring on the contact.