Method for fabricating field-effect transistor
View Patent ↗A method for fabricating complimentary metal-oxide-semiconductor field-effect transistor is disclosed. The method includes the steps of: (A) forming a first gate structure and a second gate structure on a substrate; (B) performing a first co-implantation process to define a first type source/drain extension region depth profile in the substrate adjacent to two sides of the first gate structure; (C) forming a first source/drain extension region in the substrate adjacent to the first gate structure; (D) performing a second co-implantation process to define a first pocket region depth profile in the substrate adjacent to two sides of the second gate structure; (E) performing a first pocket implantation process to form a first pocket region adjacent to two sides of the second gate structure.
1. A method for fabricating a complimentary metal-oxide-semiconductor field-effect transistor (MOSFET), comprising:
(A) forming a PMOS gate structure and an NMOS gate structure on a substrate;
(B) performing a first co-implantation process to define a p-type source/drain extension region depth profile in the substrate adjacent to two sides of the PMOS gate structure;
(C) forming a p-type source/drain extension region with p-type species in the substrate adjacent to the PMOS gate structure;
(D) performing a second co-implantation process to define a first pocket region depth profile in the substrate adjacent to two sides of the NMOS gate structure;
(E) performing a first pocket implantation process with p-type species to form a first pocket region adjacent to two sides of the NMOS gate structure;
(M) performing a second pocket implantation process to form a second pocket region adjacent to two sides of the NMOS gate structure before the step (D);
(N) performing a second pre-amorphization implantation process to amorphize the substrate adjacent to two sides of the NMOS gate structure before the step (M);
(O) forming an n-type source/drain region in the substrate after the step (E);
(P) forming an n-type source/drain extension region in the substrate adjacent to the NMOS gate structure before the step (O); and
performing sequentially the step (E), the step (P), and the step (O).
2. The method of claim 1 , wherein a species implanted in the first co-implantation process comprises carbon or fluorine.
3. The method of claim 1 , wherein a species implanted in the second co-implantation process comprises carbon or fluorine.
4. The method of claim 1 , further comprising (F) performing a first pre-amorphization implantation process to amorphize the substrate adjacent to two sides of the PMOS gate structure before the step (B).
5. The method of claim 4 , further comprising (G) performing a third pocket implantation process to form a third pocket region adjacent to two sides of the PMOS gate structure before the step (B).
6. The method of claim 5 , further comprising performing sequentially the step (G) and the step (C).
7. The method of claim 5 , further comprising performing sequentially the step (C) and the step (G).
8. The method of claim 5 , wherein a species implanted in the third pocket implantation process comprises phosphorous or arsenic.
9. The method of claim 5 , further comprising (H) forming a p-type source/drain region in the substrate after the step (C).
10. The method of claim 9 , wherein the step (H) comprises:
(1) performing an epitaxy growth process to form a semiconductor compound; and
(J) performing an ion implantation process to form the p-type source/drain region.
11. The method of claim 9 , wherein the step (H) comprises:
(K) performing an in-situ doping epitaxy growth process to form a doped semiconductor compound serving as the p-type source/drain region.
12. The method of claim 9 , wherein a species implanted in the p-type source/drain extension region, the p-type source/drain region, and the first pocket region comprises boron or BF 3 + .
13. The method of claim 9 , further comprising performing a third co-implantation process between the step (F) and the step (G), the step (G) and the step (C), or the step (C) and the step (H).
14. The method of claim 13 , wherein a species implanted in the third co-implantation process comprises carbon or fluorine.
15. The method of claim 1 , further comprising
(L) performing a fourth co-implantation process between the step (B) and the step (C).
16. The method of claim 15 , wherein a species implanted in the fourth co-implantation process comprises carbon or fluorine.
17. The method of claim 1 , wherein the second pocket implantation process comprises implanting nitrogen into the substrate for forming the second pocket region.
18. The method of claim 1 , further comprising performing a fifth co-implantation process between the step (N) and the step (M), the step (M) and the step (E), the step (E) and the step (P), or the step (P) and the step (O).
19. The method of claim 1 , further comprising:
(G) performing a third pocket implantation process to form a third pocket region adjacent to two sides of the PMOS gate structure; and
(L) performing a fourth co-implantation process, wherein the step (G), the step (B), the step (L) and the step (C) are performed sequentially.