IP Library Granted Patent US 8,659,109
Granted Patent B2
US 8,659,109 · App. 12/984,067 · Granted Feb 25, 2014

Image sensor photodiode

Inventor: François Roy (Seyssins, FR)
Assignee: STMicroelectronics (Crolles 2) SAS
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Quick Facts
Patent No.
US 8,659,109
App. No.
12/984,067
Granted
Feb 25, 2014
Kind
B2
Abstract

An image sensor including a plurality of pixels each including a charge collection region including an N-type region bounded by P-type regions and having an overlying P-type layer; and an insulated gate electrode positioned over the P-type layer and arranged to receive a gate voltage for conveying charges stored in the charge collection region through the P-type layer.

Claims (47)

1. An image sensor comprising a plurality of pixels each comprising:

a charge collection region comprising an N-type region bounded by P-type regions and having an overlying P-type layer, wherein the N-type region has a depth that is greater than a width thereof; and

an insulated gate electrode positioned directly over the overlying P-type layer and the N-type region, and arranged to receive a gate voltage, the insulated gate electrode configured to convey charges between the charge collection region and the overlying P-type layer and between the overlying P-type layer and a sensing node, wherein an entirety of the insulated gate electrode is positioned directly over the N-type region.

2. The image sensor of claim 1 , wherein one of said P-type regions is a heavily doped P-type region between said charge collection region and an isolation trench.

3. The image sensor of claim 1 , wherein said charge collection region is formed in a P-type substrate, wherein said charge collection region is bounded on at least one side by a P-type region, and wherein said P-type region has a higher doping concentration than said P-type substrate.

4. The image sensor of claim 1 , wherein the sensing node is positioned adjacent to said insulated gate electrode, and wherein said gate voltage conveys charges through the overlying P-type layer to the sensing node.

5. The image sensor of claim 4 , wherein said sensing node at least partially overhangs said charge collection region.

6. The image sensor of claim 1 , wherein the charge collection region has a depth of between 0.5 μm and 2 μm.

7. The image sensor of claim 1 , wherein the charge collection region has a width of between 0.05 μm and 0.4 μm.

8. The image sensor of claim 7 , wherein said N-type region of the charge collection region has a doping concentration in the range of 10 15 to 5×10 17 at./cm 3 .

9. The image sensor of claim 1 , wherein said P-type layer has a doping concentration of between 10 16 and 10 18 at./cm 3 .

10. The image sensor of claim 1 , wherein said P-type layer has a thickness of between 20 and 150 nm.

11. The image sensor of claim 1 , wherein each pixel further comprises a source follower transistor formed within a pixel region delimited by isolation trenches, said source follower transistor being isolated on at least one side by a shallow trench isolation.

12. An electronic device comprising the image sensor of claim 1 .

13. A mobile telephone comprising the image sensor of claim 1 .

14. A method of manufacturing an image sensor comprising forming each pixel of said image sensor by:

forming in a substrate an N-type region of a charge collection region delimited by P-type regions and an overlying P-type layer, wherein the N-type region is formed to have a depth that is greater than a width thereof; and

forming an insulated gate electrode directly over said overlying P-type layer and said N-type region, the insulated gate electrode arranged to receive a gate voltage for conveying charges between said charge collection region and said overlying P-type layer and between said overlying P-type layer and a sensing node, wherein an entirety of the insulated gate electrode is positioned directly over the N-type region.

15. The method of claim 14 , further comprising forming the sensing node in said P-type substrate adjacent to said insulated gate electrode.

16. An image sensor pixel for an image sensor, comprising:

a charge collection region comprising an N-type region formed in a P-type substrate; wherein the N-type region has a depth that is greater than a width thereof;

an insulated gate positioned in its entirety directly over the N-type region;

a P-type layer between the N-type region and the insulated gate and overlying the N-type region; and

a sensing node, wherein the insulated gate is configured to control flow of charges between the charge collection region and the overlying P-type layer and between the overlying P-type layer and the sensing node in response to a gate voltage.

17. An image sensor pixel as defined in claim 16 , further comprising a heavily-doped P-type barrier and a deep trench isolation, wherein the heavily-doped P-type barrier is located between the charge collection region and the deep trench isolation.

18. An image sensor pixel as defined in claim 16 , wherein the sensing node at least partially overlaps the N-type region.

19. An image sensor pixel as defined in claim 16 , wherein the insulated gate is a gate of a transfer transistor that controls flow of charge between the charge collection region and the sensing node.

20. An image sensor pixel as defined in claim 16 , further comprising a source follower transistor having a gate coupled to the sensing node.

21. An image sensor pixel as defined in claim 20 , wherein the source follower transistor is isolated by a shallow trench isolation.

22. An image sensor pixel as defined in claim 16 , wherein a depth of the N-type region is greater than a width of the N-type region.

23. An image sensor pixel as defined in claim 16 , wherein a width of the N-type region is in a range of 0.05 micrometer to 0.4 micrometer and a depth of the N-type region is in a range of 0.5 micrometer to 2 micrometers.

24. An image sensor pixel as defined in claim 16 , wherein the P-type layer has the same or slightly lower doping concentration than the P-type substrate.

25. An image sensor pixel as defined in claim 16 , wherein the P-type layer has a doping concentration between 10 16 and 10 18 at./cm 3 .

26. An image sensor pixel as defined in claim 16 , wherein the P-type layer has a thickness between 20 and 150 nanometers.

27. An image sensor pixel as defined in claim 16 , wherein the N-type region has a doping concentration in a range of 10 14 to 10 17 at./cm 3 .

28. An image sensor pixel as defined in claim 16 , wherein charge is transferred through a top of the N-type region.

29. A method for making an image sensor pixel of an image sensor, comprising:

forming a charge collection region comprising an N-type region in a P-type substrate,. including forming the N-type region to have a depth that is greater than a width thereof;

forming an insulated gate positioned in its entirety directly over the N-type region;

forming a P-type layer between the N-type region and the insulated gate and overlying the N-type region; and

forming a sensing node, wherein the insulated gate is configured to control flow of charges between the charge collection region and the overlying P-type layer and between the overlying P-type layer and the sensing node in response to a gate voltage.

30. A method as defined in claim 29 , further comprising forming a deep trench isolation in the substrate and forming a heavily-doped P-type barrier between the charge collection region and the deep trench isolation.

31. A method as defined in claim 29 , further comprising forming a source follower transistor in the image sensor pixel.

32. A method as defined in claim 29 , wherein forming the charge collection region comprises forming the N-type region such that a depth of the N-type region is greater than a width of the N-type region.

33. A method as defined in claim 29 , wherein forming a charge collection region comprises forming the N-type region with a width in a range of 0.05 micrometer to 0.4 micrometer and a depth in a range of 0.5 micrometer to 2 micrometers.

34. A method as defined in claim 29 , wherein forming a P-type layer comprises forming the P-type layer with a thickness in a range of 20 to 150 nanometers.

35. A method as defined in claim 29 , wherein the charge collection region is formed such that charge is transferred from the top of the N-type region.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 16, 2011
From: ROY, FRANCOIS
To: STMICROELECTRONICS (CROLLES 2) SAS
Reel/Frame 025960/0167 →
Priority Claims (1)
FR 10 50565 · Jan 28, 2010 · national
Continuity (1)
Related Publication 20110183709A1 · Jul 28, 2011