Hybrid integrated semiconductor tri-gate and split dual-gate FinFET devices and method for manufacturing

1. A method for making an integrated circuit including at least a tri-gate FinFET region and a dual-gate FinFET region, the method comprising:

providing a semiconductor on insulator (SOI) substrate, the SOI substrate comprising a semiconductor layer overlying an insulator layer, the semiconductor layer having a surface region, the surface region including the tri-gate FinFET region and the dual-gate FinFET region;

implanting impurities into the semiconductor layer for a threshold voltage adjustment;

forming a silicon nitride film overlying the surface region;

forming a nitride cap region in the dual-gate FinFET region and completely removing the silicon nitride film in the tri-gate FinFET region in a same etching process step;

etching the semiconductor layer to form a first silicon fin region in the dual-gate FinFET region and a second silicon fin region in the tri-gate FinFET region that is free of the silicon nitride film, the nitride cap region being maintained on a portion of a surface region of the first silicon fin region;

forming a gate dielectric;

depositing a polysilicon film;

planarizing the polysilicon film by chemical mechanical polishing (CMP) using the nitride cap region as a polish stop;

selectively etching the polysilicon film to form a first and a second gate electrodes of the first silicon fin region covered by the nitride cap, the first and a second gate electrodes being on opposite sides of the first silicon fin region;

selectively etching the polysilicon film to form a third gate electrode, the third gate electrode being adjacent to and overlying a portion of the second silicon fin region;

forming spacers;

implanting impurities to form source and drain regions;

forming elevated source and drain regions; and

performing backend processing.

2. The method of claim 1 , wherein the SOI substrate comprising a substrate, an oxide layer overlying the substrate, and a silicon layer overlying the oxide layer, the silicon layer including the surface region.

3. The method of claim 1 , wherein the SOI substrate comprising a substrate, an insulator layer overlying a substrate, and a silicon-germanium layer overlying the insulator layer, the silicon-germanium layer including the surface region.

4. The method of claim 1 , wherein the first silicon fin region is characterized by a width of about 5-50 nm and a height of about 5-100 nm.

5. The method of claim 1 , wherein the second silicon fin region is characterized by a width of about 5-50 nm and a height of about 5-100 nm.

6. The method of claim 1 , wherein forming a first and a second silicon fin regions further comprising annealing in an H 2 ambient at a temperature range of approximately 800-1000° C.

7. The method of claim 1 , wherein selectively etching the polysilicon film further comprises:

providing a hard mask;

patterning the hard mask;

etching the polysilicon film; and

removing the hard mask.

8. The method of claim 1 , wherein forming elevated source and drain regions further comprises:

forming a SiGe layer on the source and drain regions by selective epitaxial growth at a temperature of about 700-800° C. in an ambient of SiH 2 Cl 2 +HCl+GeH 4 .

9. The method of claim 8 , wherein the SiGe layer comprises a thickness of about 100 nm to about 500 nm and a Ge content of about 10-30%.

10. The method of claim 1 , wherein performing backend process further comprises:

depositing interlayer dielectrics, the dielectrics comprising low-k dielectrics;

forming contact regions, the contact regions comprising tungsten plugs; and

forming interconnect, the interconnect comprising copper interconnect lines.

11. The method of claim 1 , wherein depositing a polysilicon film is conducted at a temperature in a range of about 600 degrees C. to 800 degrees C.

12. The method of claim 1 , wherein the deposited polysilicon film has a thickness in a range of about 100 nm to about 500 nm.

13. The method of claim 1 , wherein implanting impurities comprises doping at a dose of 1 to 5×10 12 /cm 2 and an implant energy of 1 to 30 KeV.

14. The method of claim 1 , wherein forming a silicon nitride film comprises depositing the silicon nitride film at a temperature of about 700 degrees C. to 800 degrees C. and with a thickness in a range of about 100 nm to about 500 nm.

15. A method for making an integrated circuit including at least a tri-gate FinFET and a dual-gate FinFET, the method comprising:

providing a semiconductor on insulator (SOI) substrate, the SOI substrate comprising a semiconductor layer overlying an insulator layer, the semiconductor layer having a first region and a second region;

forming a silicon nitride film overlying the surface region;

forming a nitride cap in the first region and completely removing the silicon nitride film in the second region in a same etching step;

etching the semiconductor layer to form a first silicon fin region having a portion below the nitride cap in the first region and a second silicon fin region in the second region that is free of the silicon nitride film;

forming a gate dielectric layer;

depositing a polysilicon film;

planarizing the polysilicon film by chemical mechanical polishing (CMP) using the nitride cap region as a polish stop; and

selectively etching the polysilicon film to form a first gate electrode and a second gate electrode of the first silicon fin region covered by the nitride cap, and a third gate electrode of the second fin region;

wherein the first and second gate electrodes are on opposite sides of the first silicon fin region, and

wherein the third gate electrode is adjacent to and overlying a portion of the second silicon fin region.

16. The method of claim 15 , wherein the first region is a core logic region and the second region is in an input/output (I/O) region.

17. The method of claim 15 , further comprising annealing the first and second silicon fin regions in an H 2 ambient at a temperature ranging from about 800 degrees C. to about 1000 degrees C.

18. The method of claim 15 , wherein forming the gate dielectric layer comprises:

rapid thermal oxidation at a temperature in a range of about 700 degrees C. to about 900 degrees C. with a thickness in a range of about 0.1 nm to about 3 nm;

decoupled plasma nitridation in a nitrogen ambient; and

post nitridation anneal.