IP Library › Granted Patent US 9,111,945
Granted Patent B2
US 9,111,945 · App. 12/987,613 · Granted Aug 18, 2015

Package having ESD and EMI preventing functions and fabrication method thereof

Inventors: Tsung-Hsien Tsai (Taichung, TW); Chih-Hsien Chiu (Taichung, TW); Hsin-Lung Chung (Taichung, TW); Chien-Cheng Lin (Taichung, TW)
Assignee: Siliconware Precision Industries Co., Ltd.
H01L23/552H01L24/19H01L24/20H01L24/97H01L2224/0401H01L2224/04105H01L2224/16225H01L2224/32225H01L2224/48091H01L2224/48227H01L2224/73267H01L2224/92244H01L2224/97H01L2924/01029H01L2924/15311H01L2924/3025
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Quick Facts
Patent No.
US 9,111,945
App. No.
12/987,613
Granted
Aug 18, 2015
Kind
B2
Abstract

A package having ESD (electrostatic discharge) and EMI (electromagnetic interference) preventing functions includes: a substrate unit having a ground structure and an I/O structure disposed therein; at least a semiconductor component disposed on a surface of the substrate unit and electrically connected to the ground structure and the I/O structure; an encapsulant covering the surface of the substrate unit and the semiconductor component; and a metal layer disposed on exposed surfaces of the encapsulant and side surfaces of the substrate unit and electrically insulated from the ground structure, thereby protecting the semiconductor component against ESD and EMI so as to improve the product yield and reduce the risk of short circuits.

Claims (18)

1. A package having ESD (electrostatic discharge) and EMI (electromagnetic interference) preventing functions, comprising:

a substrate unit having a first surface and a second surface opposite to the first surface, wherein the substrate unit has a ground structure and an I/O structure disposed therein;

at least a semiconductor component disposed on the second surface of the substrate unit and electrically connected to the ground structure and the I/O structure of the substrate unit;

an encapsulant covering the second surface of the substrate unit and the semiconductor component;

a metal layer formed on exposed surfaces of the encapsulant and being in contact with side surfaces of the substrate unit without contacting the ground structure, wherein the entire metal layer is electrically insulated from the ground structure of the substrate unit by the substrate unit; and

a plurality of conductive elements disposed on the first surface of the substrate unit for electrically connecting the metal layer,

wherein the first surface of the substrate unit is formed with a plurality of first conductive pads and ESD protection pads and wherein the first conductive pads are electrically connected to the ground structure and the I/O structure, respectively.

2. The package of claim 1 , wherein the ESD protection pads are disposed around a periphery of the substrate unit.

3. The package of claim 2 , wherein the ESD protection pads are electrically connected to the ground structure.

4. The package of claim 2 , wherein the ESD protection pads are spaced from the metal layer.

5. The package of claim 2 , wherein the ESD protection pads consist of first sub-pads and second sub-pads spaced from the first sub-pads, wherein the first sub-pads are disposed on edges of the first surface of the substrate unit and flush with the side surfaces of the substrate unit.

6. The package of claim 5 , wherein the first sub-pads are electrically insulated from the ground structure of the substrate unit.

7. The package of claim 5 , wherein the second sub-pads are electrically connected to the ground structure of the substrate unit.

8. The package of claim 1 , wherein at least a portion of the ESD protection pads are disposed on edges of the first surface of the substrate unit and flush with the side surfaces of the substrate unit.

9. The package of claim 8 , wherein the portion of the ESD protection pads comprise indentations disposed at edges flush with the side surfaces of the substrate unit.

10. The package of claim 8 , wherein the portion of the ESD protection pads are electrically insulated from the ground structure of the substrate unit.

11. The package of claim 1 , wherein side surfaces of the encapsulant are flush with the side surfaces of the substrate unit.

12. The package of claim 1 , wherein the metal layer is made of one of Cu, Ni, Fe, Al and Sus (stainless steel).

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2011
From: TSAI, TSUNG-HSIEN; CHIU, CHIH-HSIEN; CHUNG, HSIN-LUNG; LIN, CHIEN-CHENG
To: SILICONWARE PRECISION INDUSTRIES CO., LTD.
Reel/Frame 025611/0185 →
Priority Claims (1)
TW 99140955 A · Nov 26, 2010 · national
Continuity (1)
Related Publication 20120133032A1 · May 31, 2012