Method of erasing a flash EEPROM memory
A method for erasing a flash EEPROM memory device is disclosed. The memory device has a first semiconductor region of one conductivity type formed within a second semiconductor region of an opposite conductivity type, source and drain regions formed from a semiconductor layer of the opposite conductivity type in the first semiconductor region, a well electrode formed from a semiconductor layer of the conductivity type inside the first semiconductor region, a charge storing layer electrically isolated from the first semiconductor region by a dielectric layer and having electric charge retention properties, and a control gate electrode electrically isolated from the charge storing layer by a inter layer of coupling dielectrics. The method comprises the steps of: applying a first voltage bias to both the well electrode and the second semiconductor region and a second bias to the control gate electrode for a duration of F/N tunneling; applying a third voltage bias to the well electrode and the second semiconductor region and a first zero voltage bias to the control gate electrode for a duration of traps depopulation; and, after the duration of traps depopulation, applying a fourth voltage bias to the control gate electrode and a second zero voltage bias to the well electrode and the second semiconductor region for a duration of traps assisted tunneling.
1. A method for erasing a flash electrically erasable, programmable, read-only memory device having a first semiconductor region of one conductivity type formed within a second semiconductor region of an opposite conductivity type, source and drain regions formed from a semiconductor layer of the opposite conductivity type in the first semiconductor region, a well electrode formed from a semiconductor layer of the conductivity type inside the first semiconductor region, a charge storing layer electrically isolated from the first semiconductor region by a dielectric layer and having electric charge retention properties, and a control gate electrode electrically isolated from the charge storing layer by a inter layer of coupling dielectrics, the method comprising the steps of:
applying a first voltage bias of positive polarity to both the well electrode and the second semiconductor region and a second voltage bias of negative polarity to the control gate electrode for a duration of F/N tunneling;
after the duration of F/N tunneling, applying a third voltage bias of positive polarity to both the well electrode and the second semiconductor region and a first zero voltage bias to the control gate electrode for a duration of traps depopulation; and
after the duration of traps depopulation, applying a fourth voltage bias of negative polarity to the control gate electrode and a second zero voltage bias to both the well electrode and the second semiconductor region for a duration of traps assisted tunneling.
2. The method of claim 1 , further comprising:
applying a third zero voltage bias to the control gate electrode, the well electrode and the second semiconductor region for a time period between the step of applying the first voltage bias and the second voltage bias and the step of applying the third voltage bias and the first zero voltage bias.
3. The method of claim 1 , wherein each of the source and drain regions is kept floating or at the same voltage as the well electrode.
4. The method of claim 1 , wherein the charge storing layer is initially in an electron-storing state.
5. The method of claim 1 , wherein the charge storing layer is in a hole-storing state after the step of applying the fourth voltage bias and the second zero voltage bias.
6. A method for erasing a flash electrically erasable, programmable, read-only memory device having a first semiconductor region of one conductivity type formed within a second semiconductor region of an opposite conductivity type, source and drain regions formed from a semiconductor layer of the opposite conductivity type in the first semiconductor region, a well electrode formed from a semiconductor layer of the conductivity type inside the first semiconductor region, a charge storing layer electrically isolated from the first semiconductor region by a dielectric layer and having electric charge retention properties, and a control gate electrode electrically isolated from the charge storing layer by a inter layer of coupling dielectrics, the method comprising the steps of:
applying a first voltage bias of negative polarity to both the well electrode and the second semiconductor region and applying a first zero voltage bias to the control gate electrode for a duration of traps depopulation;
after the duration of traps depopulation, applying a second voltage bias of positive polarity to the control gate electrode and a second zero voltage bias to both the well electrode and the second semiconductor region for a duration of traps assisted tunneling; and
after the duration of traps assisted tunneling, applying a third voltage bias of positive polarity to the control gate electrode and a fourth voltage bias of negative polarity to both the well electrode and the second semiconductor region for a duration of F/N tunneling.
7. The method of claim 6 , further comprising:
applying a third zero voltage bias to the control gate electrode, the well electrode and the second semiconductor region for a time period between the step of applying the second voltage bias and the second zero voltage bias and the step of applying the third voltage bias and the fourth voltage bias.
8. The method of claim 6 , wherein each of the source and drain regions is kept floating or at the same voltage as the well electrode.
9. The method of claim 6 , wherein the charge storing layer is initially in a hole-storing state.
10. The method of claim 6 , wherein the charge storing layer is in an electron-storing state after the step of applying the second voltage bias and the second zero voltage bias.
11. A method for erasing a flash electrically erasable, programmable, read-only memory device having a first semiconductor region of one conductivity type formed within a second semiconductor region of an opposite conductivity type, source and drain regions formed from a semiconductor layer of the opposite conductivity type in the first semiconductor region, a well electrode formed from a semiconductor layer of the conductivity type inside the first semiconductor region, a charge storing layer electrically isolated from the first semiconductor region by a dielectric layer and having electric charge retention properties, and a control gate electrode electrically isolated from the charge storing layer by a inter layer of coupling dielectrics, the method comprising the steps of:
applying a first voltage bias to both the well electrode and the second semiconductor region and a second voltage bias to the control gate electrode for a duration of F/N tunneling;
applying a third voltage bias to both the well electrode and the second semiconductor region and a first zero voltage bias to the control gate electrode for a duration of traps depopulation; and
after the duration of traps depopulation, applying a fourth voltage bias to the control gate electrode and a second zero voltage bias to both the well electrode and the second semiconductor region for a duration of traps assisted tunneling.
12. The method of claim 11 , wherein each of the source and drain regions is kept floating or at the same voltage as the well electrode.
13. The method of claim 11 , wherein a polarity of the first voltage bias is opposite to that of the second voltage bias; and wherein a polarity of the third voltage bias is the same as that of the first voltage bias but opposite to that of the fourth voltage bias.
14. The method of claim 11 , wherein when the charge storing layer is initially in an electron-storing state, the step of applying the first voltage bias and the second voltage bias is followed by the step of applying the third voltage bias and the first zero voltage bias.
15. The method of claim 14 , further comprising:
applying a third zero voltage bias to the control gate electrode, the well electrode and the second semiconductor region for a time period between the step of applying the first voltage bias and the second voltage bias and the step of applying the third voltage bias and the first zero voltage bias.
16. The method of claim 11 , wherein when the charge storing layer is initially in a hole-storing state, the step of applying the fourth voltage bias and the second zero voltage bias is followed by the step of applying the first voltage bias and the second voltage bias.
17. The method of claim 16 , further comprising:
applying a third zero voltage bias to the control gate electrode, the well electrode and the second semiconductor region for a time period between the step of applying the fourth voltage bias and the second zero voltage bias and the step of applying the first voltage bias and the second voltage bias.