Chip package and fabrication method thereof
View Patent ↗A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package contains a semiconductor substrate having a chip. A packaging layer is disposed over the semiconductor substrate. A spacer is disposed between the semiconductor substrate and the packaging layer, wherein a side surface consisting of the semiconductor substrate, the spacer and the packaging layer has a recess section. The method includes forming a plurality of spacers between a plurality of chips of a semiconductor wafer and a packaging layer, wherein each spacer corresponding to each chip is separated from each other and the spacer is shrunk inward from an edge of the chip to form a recess section and dicing the semiconductor wafer along a scribe line between any two adjacent chips to form a plurality of chip packages.
1. A chip package, comprising:
a chip having a semiconductor substrate, wherein the semiconductor substrate has at least a conductive pad that is not exposed on a surface of the semiconductor substrate;
a packaging layer disposed over the semiconductor substrate; and
a spacer disposed between the semiconductor substrate and the packaging layer, wherein a side surface is defined by the semiconductor substrate, the spacer and the packaging layer, and wherein the side surface has a recess section located at the spacer; and
a seal ring disposed outside of the conductive pad, wherein the conductive pad and the seal ring overlap with the spacer.
2. The chip package as claimed in claim 1 , wherein the recess section surrounds the spacer to form a ring-shaped recess section.
3. The chip package as claimed in claim 1 , wherein the spacer has a shape of a rectangle and the recess section is disposed at each corner of the rectangle, each side of the rectangle or combinations thereof.
4. The chip package as claimed in claim 1 , wherein the recess section is located between the semiconductor substrate and the packaging layer.
5. The chip package as claimed in claim 4 , further comprising:
a peripheral bonding pad area and a device area, wherein the peripheral bonding pad area surrounds the device area;
a plurality of conductive pads disposed on the peripheral bonding pad area; and
the seal ring disposed on the peripheral bonding pad area, surrounding the conductive pads.
6. The chip package as claimed in claim 5 , wherein the seal ring is located in an area of the spacer.
7. A chip package, comprising:
a chip having a semiconductor substrate;
a packaging layer disposed over the semiconductor substrate;
a spacer disposed between the semiconductor substrate and the packaging layer, wherein a side surface is defined by the semiconductor substrate, the spacer and the packaging layer, and wherein the side surface has a recess section located at the spacer;
a peripheral bonding pad area and a device area, wherein the peripheral bonding pad area surrounds the device area;
a plurality of conductive pads disposed on the peripheral bonding pad area
a seal ring disposed on the peripheral bonding pad area, surrounding the conductive pads;
a through hole disposed on a surface of the semiconductor substrate to expose at least one of the plurality of conductive pads;
an insulating layer disposed on the surface of the semiconductor substrate and extending to a sidewall of the through hole;
a conductive trace layer disposed on the insulating layer and extending to a bottom of the through hole for electrically connecting to the at least one of the plurality of conductive pads;
a passivation layer disposed to cover the conductive trace layer and the insulating layer, and having an opening to expose a portion of the conductive trace layer; and
a conductive bump disposed in the opening of the passivation layer for electrically connecting to the conductive trace layer.
8. The chip package as claimed in claim 1 , further comprising a cavity formed between the packaging layer and the chip of the semiconductor substrate, wherein the cavity is surrounded by the spacer.
9. The chip package as claimed in claim 1 , wherein the material of the spacer comprises a photosensitive insulating material.
10. The chip device package as claimed in claim 1 , further comprising an adhesive layer disposed between the spacer and the semiconductor substrate or between the spacer and the packaging layer.
11. The chip package as claimed in claim 3 , wherein the recess section is disposed at each corner of the spacer to form an L-shaped opening at each corner of the spacer.
12. The chip package as claimed in claim 3 , wherein the recess section is disposed at each side of the spacer to form a rectangular opening at each side of the spacer.
13. The chip package as claimed in claim 1 , wherein the seal ring is disposed between the side surface and the conductive pad, at near a periphery of the substrate.
14. A chip package, comprising:
a semiconductor substrate including a chip, wherein the semiconductor substrate has at least a conductive pad that is not exposed on a surface of the semiconductor substrate;
a packaging layer disposed over the semiconductor substrate; and
a spacer disposed between the semiconductor substrate and the packaging layer, wherein the semiconductor layer, the spacer and the packaging layer define a side surface, and wherein a recess is defined on the side surface at a location between the semiconductor layer and the packaging layer; and
a seal ring disposed between the side surface and the conductive pad, at near a periphery of the substrate, wherein the conductive pad and the seal ring overlap with the spacer.
15. The chip package as claimed in claim 14 , wherein the spacer is shrunk inward from the side surface to form the recess.