A display panel for displaying an image is provided with a plurality of pixels arranged in a matrix. Each pixel includes one or more units each including a plurality of subunits. Each subunit includes a transistor in which an oxide semiconductor layer which is provided so as to overlap a gate electrode with a gate insulating layer interposed therebetween, a pixel electrode which drives liquid crystal connected to a source or a drain of the transistor, a counter electrode which is provided so as to face the pixel electrode, and a liquid crystal layer provided between the pixel electrode and the counter electrode. In the display panel, a transistor whose off current is lower than 10 zA/μm at room temperature per micrometer of the channel width and off current of the transistor at 85° C. can be lower than 100 zA/μm per micrometer in the channel width.
1. A display device comprising:
a first transistor, one of a source electrode and a drain electrode of the first transistor being connected to be supplied with a common potential; and
a plurality of pixels provided in a matrix, the plurality of pixels each comprising one or more units, each unit comprising a plurality of subunits,
wherein the plurality of subunits each comprise:
a second transistor, one of a source electrode and a drain electrode of the second transistor being electrically connected to a source line; and
a liquid crystal element electrically connected to another of the source electrode and the drain electrode of the first transistor and another of the source electrode and the drain electrode of the second transistor,
wherein each of the first transistor and the second transistor comprises an oxide semiconductor layer, and
wherein an off current per micrometer of a channel width of each of the first transistor and the second transistor is lower than 100 zA/μm at 85° C. in a range of a voltage for driving liquid crystal molecules of the liquid crystal element.
2. The display device according to claim 1 , further comprising a lighting unit adjacent to the plurality of pixels,
wherein the lighting unit includes a light-emitting diode or an organic electroluminescence element.
3. The display device according to claim 1 , further comprising:
a first alignment film and a second alignment film,
wherein the liquid crystal element is interposed between the first alignment film and the second alignment film.
4. The display device according to claim 1 , wherein an alignment mode of liquid crystal molecules of the liquid crystal element is any one of a twisted nematic (TN), a vertical alignment (VA) mode, a multi-domain vertical alignment (MVA) mode, an in-plane switching (IPS) mode, a continuous pinwheel alignment (CPA) mode, and a patterned vertical alignment (PVA) mode.
5. The display device according to claim 1 , wherein a liquid crystal phase of the liquid crystal element is any one of a nematic phase, a smectic phase, a cholesteric phase, and a blue phase.
6. The display device according to claim 1 , wherein the source electrode and the drain electrode of the second transistor each comprise metal nitride.
7. The display device according to claim 1 , wherein the source electrode and the drain electrode of the second transistor each comprise tungsten nitride, titanium nitride, or molybdenum nitride.
8. The display device according to claim 1 , wherein a field-effect mobility of the second transistor in an on state is higher than or equal to 10 cm 2 /Vsec and lower than or equal to 150 cm 2 /Vsec.
9. The display device according to claim 1 , wherein an off current per micrometer of a channel width of each of the first transistor and the second transistor is lower than 10 zA/μm at room temperature in a range of a voltage for driving liquid crystal molecules of the liquid crystal element.
10. The display device according to claim 1 , wherein a channel formation region of the oxide semiconductor layer includes an intrinsic oxide semiconductor or a substantially intrinsic oxide semiconductor.
11. The display device according to claim 1 ,
wherein each of the plurality of the subunits further comprises a storage capacitor,
wherein a first terminal of the storage capacitor is electrically connected to the other of the source electrode and the drain electrode of the first transistor, and
wherein a second terminal of the storage capacitor is electrically connected to the other of the source electrode and the drain electrode of the second transistor.
12. A display device comprising:
a first transistor, one of a source electrode and a drain electrode of the first transistor being connected to be supplied with a common potential;
a pixel portion in which a plurality of pixels are provided in a matrix, the plurality of pixels each comprising one or more units, each unit comprising a plurality of subunits; and
a driver circuit portion electrically connected to the pixel portion, the driver circuit portion being configured to apply an image signal to a selected pixel of the plurality of pixels,
wherein the plurality of subunits each comprise:
a second transistor, one of a source electrode and a drain electrode of the second transistor being electrically connected to a source line; and
a liquid crystal element electrically connected to another of the source electrode and the drain electrode of the first transistor and another of the source electrode and the drain electrode of the second transistor,
wherein each of the first transistor and the second transistor comprises an oxide semiconductor layer, and
wherein an off current per micrometer of a channel width of each of the first transistor and the second transistor is lower than 100 zA/μm at 85° C. in a range of a voltage for driving liquid crystal molecules of the liquid crystal element.
13. The display device according to claim 12 , further comprising a lighting unit adjacent to the plurality of pixels,
wherein the lighting unit includes a light-emitting diode or an organic electroluminescence element.
14. The display device according to claim 12 , further comprising:
a first alignment film and a second alignment film,
wherein the liquid crystal element is interposed between the first alignment film and the second alignment film.
15. The display device according to claim 12 , wherein an alignment mode of liquid crystal molecules of the liquid crystal element is any one of a twisted nematic (TN), a vertical alignment (VA) mode, a multi-domain vertical alignment (MVA) mode, an in-plane switching (IPS) mode, a continuous pinwheel alignment (CPA) mode, and a patterned vertical alignment (PVA) mode.
16. The display device according to claim 12 , wherein a liquid crystal phase of the liquid crystal element is any one of a nematic phase, a smectic phase, a cholesteric phase, and a blue phase.
17. The display device according to claim 12 , wherein the source electrode and the drain electrode of the second transistor each comprise metal nitride.
18. The display device according to claim 12 , wherein the source electrode and the drain electrode of the second transistor each comprise tungsten nitride, titanium nitride, or molybdenum nitride.
19. The display device according to claim 12 , wherein a field-effect mobility of the second transistor in an on state is higher than or equal to 10 cm 2 /Vsec and lower than or equal to 150 cm 2 /Vsec.
20. The display device according to claim 12 , wherein an off current per micrometer of a channel width of each of the first transistor and the second transistor is lower than 10 zA/μm at room temperature in a range of a voltage for driving liquid crystal molecules of the liquid crystal element.
21. The display device according to claim 12 , wherein a channel formation region of the oxide semiconductor layer includes an intrinsic oxide semiconductor or a substantially intrinsic oxide semiconductor.
22. The display device according to claim 12 ,
wherein each of the plurality of the subunits further comprises a storage capacitor,
wherein a first terminal of the storage capacitor is electrically connected to the other of the source electrode and the drain electrode of the first transistor, and
wherein a second terminal of the storage capacitor is electrically connected to the other of the source electrode and the drain electrode of the second transistor.
23. A display device comprising:
a first transistor, one of a source electrode and a drain electrode of the first transistor being connected to be supplied with a common potential;
a pixel portion in which a plurality of pixels are provided in a matrix, the plurality of pixels each comprising one or more units, each unit comprising a plurality of subunits; and
a driver circuit portion electrically connected to the pixel portion, the driver circuit portion being configured to select a first operation mode in which an image signal is applied to a selected pixel of the plurality of pixels to display an image, or a second operation mode in which an application of an image signal is stopped and an image is held,
wherein the plurality of subunits each comprise:
a second transistor, one of a source electrode and a drain electrode of the second transistor being electrically connected to a source line; and
a liquid crystal element electrically connected to another of the source electrode and the drain electrode of the first transistor and another of the source electrode and the drain electrode of the second transistor,
wherein each of the first transistor and the second transistor comprises an oxide semiconductor layer, and
wherein an off current per micrometer of a channel width of each of the first transistor and the second transistor is lower than 100 zA/μm at 85° C. in a range of a voltage for driving liquid crystal molecules of the liquid crystal element.
24. The display device according to claim 23 , further comprising a lighting unit adjacent to the plurality of pixels,
wherein the lighting unit includes a light-emitting diode or an organic electroluminescence element.
25. The display device according to claim 23 , further comprising:
a first alignment film and a second alignment film,
wherein the liquid crystal element is interposed between the first alignment film and the second alignment film.
26. The display device according to claim 23 , wherein an alignment mode of liquid crystal molecules of the liquid crystal element is any one of a twisted nematic (TN), a vertical alignment (VA) mode, a multi-domain vertical alignment (MVA) mode, an in-plane switching (IPS) mode, a continuous pinwheel alignment (CPA) mode, and a patterned vertical alignment (PVA) mode.
27. The display device according to claim 23 , wherein a liquid crystal phase of the liquid crystal element is any one of a nematic phase, a smectic phase, a cholesteric phase, and a blue phase.
28. The display device according to claim 23 , wherein the source electrode and the drain electrode of the second transistor each comprise metal nitride.
29. The display device according to claim 23 , wherein the source electrode and the drain electrode of the second transistor each comprise tungsten nitride, titanium nitride, or molybdenum nitride.
30. The display device according to claim 23 , wherein a field-effect mobility of the second transistor in an on state is higher than or equal to 10 cm 2 /Vsec and lower than or equal to 150 cm 2 /Vsec.
31. The display device according to claim 23 , wherein an off current per micrometer of a channel width of each of the first transistor and the second transistor is lower than 10 zA/μm at room temperature in a range of a voltage for driving liquid crystal molecules of the liquid crystal element.
32. The display device according to claim 23 , wherein a channel formation region of the oxide semiconductor layer includes an intrinsic oxide semiconductor or a substantially intrinsic oxide semiconductor.
33. The display device according to claim 23 ,
wherein each of the plurality of the subunits further comprises a storage capacitor,
wherein a first terminal of the storage capacitor is electrically connected to the other of the source electrode and the drain electrode of the first transistor, and
wherein a second terminal of the storage capacitor is electrically connected to the other of the source electrode and the drain electrode of the second transistor.