System and method for addressing threshold voltage shifts of memory cells in an electronic product
View Patent ↗Methods and systems for addressing threshold voltage shifts of memory cells. A method includes reading a pattern of data from a first plurality of memory cells, comparing the read of the pattern of data with a known pattern of data using a reference, and if the read of the pattern of data and the known pattern of data do not match, adjusting the reference to find a reference level that results in a matching of a read of the pattern of data and the known pattern of data. Thereafter, trim sector data is read into a second plurality of memory cells using the adjusted reference level.
1. A method for addressing threshold voltage shifts of memory cells, comprising:
reading a pattern of data from a first plurality of memory cells, wherein said reading is a first read of said data;
using a reference, comparing said read of said pattern of data from said first plurality of memory cells with a known pattern of data;
if said read of said pattern of data from said first plurality of memory cells and said known pattern of data do not match, adjusting said reference to find an adjusted reference level that results in a matching of a read of said pattern of data and said known pattern of data; and
reading trim sector data into a second plurality of memory cells using said adjusted reference level.
2. The method of claim 1 wherein said adjusting said reference to find an adjusted reference level is controlled by an algorithm.
3. The method of claim 1 wherein said reference comprises a digital current source provided reference.
4. The method of claim 3 wherein said digital current source is controlled by a microcontroller.
5. The method of claim 1 wherein said reading a pattern of data from said first plurality of memory cells comprises reading from a flash memory device.
6. The method of claim 1 wherein said second plurality of memory cells comprises memory cells of an SRAM.
7. The method of claim 1 wherein said reading said trim sector data into a second plurality of memory cells comprises reading said trim sector data from a flash memory device into an SRAM.
8. A system for addressing threshold voltage shifts of memory cells, comprising:
a reading component for executing a read of a pattern of data stored in a first plurality of memory cells, wherein said read is a first read of said data;
a comparing component for comparing said read of said pattern of data stored in said first plurality of memory cells with a known pattern of data using a reference;
an adjusting component for adjusting said reference until a read of said pattern of data stored in said first plurality of memory cells and said known pattern of data matches; and
a trim providing component for reading trim data into a second plurality of memory cells using said adjusted reference.
9. The system of claim 8 , wherein said comparing component receives an input from a current source and a memory device.
10. The system of claim 8 , wherein said adjusting component comprises an algorithm.
11. The system of claim 8 , wherein said adjusting component comprises an algorithm and a microcontroller.
12. The system of claim 8 , wherein said reading component executes a read of said pattern of data from a flash memory device.
13. The system of claim 8 , wherein said pattern of data comprises microcode that is stored in said first plurality of memory cells.
14. The system of claim 8 , wherein said read of said pattern of data is one of a start up read or a non start up read.
15. A device, comprising:
memory cells; and
a system for addressing threshold voltage shifts of memory cells, comprising:
a reading component for executing a read of a known pattern of data stored in a plurality of memory cells of said device, wherein said read is a first read of said data;
comparing component for comparing said read of said known pattern of data stored in said plurality of memory cells with expected read values corresponding to said known pattern of data using said reference;
an adjusting component for adjusting said reference until a read of said pattern of data stored in said plurality of memory cells and said expected read values corresponding to said known pattern of data matches; and
a trim providing component for reading trim data into a second plurality of memory cells using said adjusted reference.
16. The device of claim 15 , wherein said comparing component receives an input from a current source and a memory device.
17. The device of claim 15 , wherein said adjusting component comprises an algorithm.
18. The device of claim 15 , wherein said adjusting component comprises an algorithm and a microcontroller.
19. The device of claim 15 , wherein said reading component executes a read of said pattern of data from a flash memory device.
20. The device of claim 15 , wherein said pattern of data comprises microcode that is stored in said plurality of memory cells.