High speed, high resolution, high precision voltage source/AWG system for ATE

1. A method for compensating a linearity error of a dual digital-to-analog converter, comprising:

receiving a digital data signal, comprising a plurality of bits, the digital data signal indicating a voltage signal to be generated, said plurality of bits representing a set of consecutive bits being confined within a highest bit and a lowest bit;

applying a high-bit-array to a first digital-to-analog converter, said high-bit-array being composed of a consecutive sub-set of the plurality of bits of the digital data signal, the sub-set including the highest bit of the digital data signal;

using at least a part of a correction data of a look-up-table for manipulating at least a part of a low-bit-array, being composed of a consecutive sub-set of the plurality of bits of the digital data signal, the sub-set including the lowest bit of the digital data signal, wherein the manipulation of the at least a part of the low-bit-array comprises:

multiplying the at least a part of a low-bit-array by at least a first part of a correction data of the look-up-table, thereby providing a first result,

adding at least a part of the achieved first result and at least a second part of the correction data of the look-up-table, thereby providing a second result, and

applying the second result to a second digital-to-analog converter.

2. The method according to claim 1 , wherein

the first digital-to-analog converter and the second digital-to-analog converter convert their respective received digital data into a first analog signal and a second analog signal.

3. The method according to claim 1 , wherein

the high-bit-array and the low-bit-array share at least one common bits of the digital data signal.

4. The method according to claim 1 , wherein

the look-up-table is composed of at least two sub-look-up, wherein

the first part of the correction data is provided by a first sub-look-up-table of the at least two sub-look-up-tables, and

the second part of the correction data is provided by a second sub-look-up-table of the at least two sub-look-up-tables.

5. The method according to claim 1 , further comprising:

adding the first analog signal and the second analog signal, thereby providing a third result; and

converting the third result into an analog voltage signal.

6. The method according to claim 5 , further comprising

determining the converted analog voltage signal.

7. An apparatus for compensating a linearity error of a dual digital-to-analog converter, comprising

a compensating section for compensating a linearity error of a dual digital-to-analog converter adapted to operate according to a method according to claim 1 .

8. The apparatus according to claim 7 , further comprising

a first digital-to-analog converter and a second digital-to-analog converter.

9. The apparatus according to claim 8 , wherein

each of said first digital-to-analog converter and said second digital-to-analog converter when in operation provides at least 50 Msps.

10. The apparatus according to claim 8 , wherein

said first digital-to-analog converter and said second digital-to-analog converter are having each a parallel input, wherein an input to a digital-to-analog converter is a one or more bit input.

11. The apparatus according to claim 8 , wherein

said first digital-to-analog converter and said second digital-to-analog converter are arranged on the same die.