Method for producing a semiconductor wafer composed of silicon with an epitaxially deposited layer
View Patent ↗Semiconductor wafers composed of silicon with an epitaxially deposited layer, are prepared by: placing a dummy wafer on a susceptor of an epitaxy reactor; conducting an etching gas through the epitaxy reactor in order to remove residues on surfaces in the epitaxy reactor through the action of the etching gas; conducting a first deposition gas through the epitaxy reactor in order to deposit silicon on surfaces in the epitaxy reactor; replacing the dummy wafer by a substrate wafer composed of silicon; and conducting a second deposition gas through the epitaxy reactor in order to deposit an epitaxial layer on the substrate wafer.
1. A method for producing a silicon semiconductor wafer with an epitaxially deposited layer, comprising
placing a dummy wafer on a susceptor of an epitaxy reactor, wherein the dummy wafer consists of silicon or comprises silicon or silicon carbide, and is covered with an oxide layer on at least the rear side;
conducting an etching gas containing hydrogen chloride through the epitaxy reactor in order to remove residues on surfaces in the epitaxy reactor through the action of the etching gas;
conducting a first deposition gas through the epitaxy reactor to deposit silicon on surfaces in the epitaxy reactor;
replacing the dummy wafer by a silicon substrate wafer; and
conducting a second deposition gas through the epitaxy reactor to deposit an epitaxial layer on the substrate wafer.
2. The method of claim 1 , comprising
depositing an epitaxial layer on at least 2 to 24 further substrate wafers, without the dummy wafer being placed on the susceptor in the interim.
3. The method of claim 1 , wherein the oxide layer is an LTO layer.
4. The method of claim 1 , wherein the dummy wafer is reused.
5. The method of claim 4 , wherein the LTO layer has a thickness of from 100 nm to 40,000 nm.
6. The method of claim 1 , wherein the dummy wafer and the silicon substrate are each supported only at the edges of the wafer.
7. The method of claim 6 , wherein the edges of the wafers bear on a ring comprising silicon carbide which bears upon the susceptor.
8. The method of claim 6 , wherein the edges of the wafer bear on a ledge in a one-part susceptor.
9. The method of claim 1 , wherein the susceptor has a gas permeable structure.
10. The method of claim 1 , wherein the reactor is at a temperature in the range of 1050° C. to 1200° C. during contact with the etching gas.
11. The method of claim 1 , wherein the dummy wafer comprises silicon carbide.
12. The method of claim 1 , wherein the dummy wafer comprises silicon carbide and the oxide layer is an LTO layer.