Test module and a test method for reading a number of fails for a device under test (DUT)

1. A test module that tests a device under test, comprising:

a pattern generating section that generates a test pattern supplied to the device under test, based on a pattern program;

a comparing section that compares an output pattern output by the device under test to which the test pattern is supplied and an expected value pattern corresponding to the test pattern and outputs a comparison result;

a fail counter that receives the comparison result output by the comparing section and counts the number of times the comparing section indicates a mismatch between the output pattern and the expected value pattern;

a check counter that receives the comparison result output by the comparing section and counts the number of comparison bits, which are the bits for which the comparing section compares the output pattern and the expected value pattern; and

a control section that controls operation of the fail counter and the check counter according to control instructions in the pattern program.

2. The test module according to claim 1 , wherein

the comparing section detects a designated event m the output pattern or the expected value pattern,

the test module further comprises an event counter that counts the number of times that the comparing section detects the event, and

the control section further controls operation of the event counter according to the control instructions.

3. The test module according to claim 2 , further comprising a control table that records, in association with control codes, control data controlling operation of the fail counter, the check counter, and the event counter, Wherein

the control section acquires from the control table the control data associated with the control code designated by the control instructions, and controls the counters according to the acquired control data.

4. The test module according to claim 3 , further comprising registers that temporarily store values of the counters and a fail memory that stores the values of the counters, wherein

the control section resets the counters based on reset data included in the control data, sets the values of the counters in the registers based on lock data included in the control data, and writes the values set in the registers to the fail memory based on store data included in the control data.

5. The test module according to claim 3 , wherein

the control table includes a plurality of binary data in which upper bits, intermediate bits, and lower bits are allocated respectively to different members of the group consisting of the control data controlling operation of the event counter, the control data controlling operation of the fail counter, and the control data controlling operation of the check counter.

6. The test module according to claim 2 , wherein

the control section stops operation of the fail counter, the check counter, or the event counter as desired.

7. The test module according to claim 2 , wherein

a fail counter, a check counter, and an event counter are provided fur each channel that outputs or receives the test pattern or the output pattern to or from the device under test.

8. The test module according to claim 2 , comprising a plurality of the fail memories that store the values of the fail counter, the check counter, and the event counter, wherein

the plurality of fail memories are provided, respectively to the fail counter, the check counter, and the event counter.

9. The test module according to claim 2 , comprising a plurality of the fail memories that store the values of the fail counter, the check counter, and the event counter, wherein

the plurality of fail memories are provided respectively to channels that output or receive the test pattern or the output pattern to or from the device under test.

10. The test module according to claim 1 , further comprising a calculating section that calculates an error rate based on values of the fail counter and the check counter.

11. A test method for testing a device under test, comprising:

generating a test pattern supplied to the device under test, based on a pattern program;

comparing an output pattern output by the device under test to which the test pattern is supplied and an expected value pattern corresponding to the test pattern to output a comparison result;

counting the number of times the comparing indicates a mismatch between the output pattern and the expected value pattern based on the comparison result output in the comparing;

counting the number of comparison bits, which are bits for which the output pattern is compared to the expected value pattern based on the comparison result output in the comparing; and

controlling the counting the number of times and the counting the number of comparison bits according to control instructions in the pattern program.

12. The test method according to claim 11 , wherein

the comparing includes detecting a designated event in the output pattern or the expected value pattern,

the test method further comprises counting the number of times the event is detected, and

the controlling further includes controlling the counting of the number of times the event is detected according to the control instructions included in the pattern program.

13. The test method according to claim 12 , further comprising storing in a control table, in association with control codes, control data controlling the operations performed when counting the number of times the comparing indicates a mismatch, counting the number of comparison bits, and counting the number of times the event is detected, wherein

the controlling includes acquiring from the control table the control data associated with the control code designated by the control instructions, and controlling the counting operations according to the acquired control data.

14. The test method according to claim 11 , further comprising, calculating. an error rate based on count values from counting the number of times the comparing indicates a mismatch and counting the number of comparison bits.