IP Library Granted Patent US 8,140,741
Granted Patent B2
US 8,140,741 · App. 13/016,529 · Granted Mar 20, 2012

Semiconductor storage device and control method thereof

Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 8,140,741
App. No.
13/016,529
Granted
Mar 20, 2012
Kind
B2
Abstract

According to one embodiment, a semiconductor storage device comprises a main memory, a request issue module, a delay module, and an access module. The main memory is configured to store candidate information for determining a compaction candidate for a nonvolatile memory. The request issue module is configured to issue an access request for the candidate information in the main memory. The delay module is configured to delay the access request issued from the request issue module. The access module is configured to access the candidate information in the main memory based on an access request delayed by the delay module.

Claims (27)

1. A semiconductor storage device comprising:

a main memory configured to store candidate information for determining a compaction candidate for a nonvolatile memory;

a request issue module configured to issue a first access request for the main memory for searching for the candidate information;

a delay module configured to delay the first access request issued from the request issue module by a first time in accordance with an access frequency of the main memory;

an arbitration module configured to perform arbitration of an access request and

an access module configured to access the candidate information in the main memory based on the first access request delayed by the first time by the delay module when the first access request is given a right by the arbitration module.

2. The device of claim 1 , further comprising:

an acknowledgment issue module configured to issue a termination acknowledgment for the access by the access module, and

wherein the termination acknowledgement issued by the acknowledgment issue module is returned to the request issue module after being delayed by a second time by the delay module in accordance with the access frequency of the main memory.

3. The device of claim 1 , further comprising:

a detection module configured to detect an access frequency of the main memory, and

wherein the first delay time and the second delay time are set long when the access frequency detected by the detection module is higher than a predetermined value, and the first delay time and the second delay time are set shorter when the access frequency detected by the detection module is not higher than the predetermined value.

4. The device of claim 2 , wherein the first delay time is different from the second delay time.

5. The device of claim 2 , wherein the first delay time is equal to the second delay time.

6. A method of controlling a semiconductor storage device comprising a main memory configured to store candidate information for determining a compaction candidate for a nonvolatile memory, the method comprising:

issuing a first access request for the main memory for searching for the candidate information;

delaying the issued first access request by a first time in accordance with an access frequency of the main memory;

performing arbitration of an access request and

accessing the candidate information in the main memory based on the first access request delayed by the first time when the first access request is given a right by the arbitration.

7. The method of claim 6 , further comprising:

issuing a termination acknowledgment for the first access, and

returning the issued termination acknowledgment to a source of the first access request after being delayed by a second time in accordance with the access frequency of the main memory.

8. The method of claim 6 , further comprising:

detecting an access frequency of the main memory, and

wherein the first delay time and the second delay time are increased when the detected access frequency is higher than a predetermined value, and the first delay time and the second delay time are decreased when the detected access frequency is not higher than the predetermined value.

9. The method of claim 7 , wherein the first delay time is different from the second delay time.

10. The method of claim 7 , wherein the first delay time is equal to the second delay time.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 28, 2011
From: SUZUKI, HIROTAKA
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 025717/0573 →
Priority Claims (1)
JP 2010-019545 · Jan 29, 2010 · national
Continuity (1)
Related Publication 20110191528A1 · Aug 4, 2011