Planar microshells for vacuum encapsulated devices and damascene method of manufacture

1. A method of forming a microshell, the method comprising:

forming a perforated pre-sealing layer to partially enclose a chamber on a substrate, at least one perforation being defined in the perforated pre-sealing layer;

forming a sealing layer on the pre-sealing layer to close the perforation by:

forming a non-hermetic occluding layer to occlude the perforation, and

forming a metal hermetic layer to seal the perforation;

forming a conductive layer extending down an outer sidewall of the microshell; and

electrically coupling the hermetic layer to the conductive layer.

2. The method of claim 1 ,

wherein the perforation has an aspect ratio greater than 8:1 height to width ratio.

3. The method of claim 2 , further comprising:

forming a non-planar sacrificial layer over the substrate;

forming the pre-sealing layer over the non-planar sacrificial layer;

forming the perforation by planarizing the pre-sealing layer to perforate the pre-sealing layer with a topographic feature of the non-planar sacrificial layer;

removing the non-planar sacrificial layer through the perforation to form the chamber around a device under the pre-sealing layer; and

sealing the pre-sealing layer.

4. The method of claim 2 , wherein the perforation is above the chamber.

5. The method of claim 2 , wherein the perforation in the pre-sealing layer is offset from a released MEMS structure enclosed within the chamber.

6. The method of claim 1 , further comprising providing a grounded metal-insulator microshell to encapsulate a released interconnect structure by:

forming the perforated pre-sealing layer to partially enclose the chamber on the substrate with the released interconnect structure enclosed by the chamber; and

forming the conductive layer on the sealing layer, the conductive layer being electrically coupled to a ground ring adjacent to the metal-insulator microshell.

7. The method of claim 6 , further comprising providing a CMOS device on the substrate electrically coupled to the released interconnect structure.

8. The method of claim 7 , wherein the released interconnect structure is a MEMS resonator.

9. The method of claim 8 , wherein the CMOS device is a timing circuit including a voltage controlled oscillator and a phase-lock loop.

10. The method of claim 6 , wherein the released interconnect structure forms a one-port capacitor with the grounded metal-insulator microshell.

11. The method of claim 6 , wherein the released interconnect structure forms an inductor.

12. The method of claim 6 , wherein the released interconnect structure forms a microstrip or coplanar waveguide transmission line.

13. The method of claim 6 , wherein the released interconnect structure is a MEMS resonator.

14. The method of claim 13 , wherein the released interconnect structure is a MEMS resonator that forms a capacitor with the grounded metal-insulator microshell.

15. The method of claim 6 , wherein the released interconnect structure forms a microstrip or coplanar waveguide transmission line.

16. A method of forming a microshell comprising:

forming a non-planar sacrificial layer over a substrate;

forming a pre-sealing layer over the non-planar sacrificial layer;

planarizing the pre-sealing layer to perforate the pre-sealing layer with a topographic feature of the non-planar sacrificial layer to define at least one perforation in the perforated pre-sealing layer;

removing the non-planar sacrificial layer through the perforation to form a chamber around a device under the pre-sealing layer;

sealing the pre-sealing layer;

etching through the sealing layer to expose a metal ground ring adjacent to the chamber; and

depositing a conductive layer on the sealing layer and the metal ground ring to electrically ground the microshell.

17. The method of claim 16 , wherein the sacrificial material is formed over a structural component of a MEMS.

18. The method of claim 16 , wherein forming the non-planar sacrificial layer further comprises:

forming a sacrificial material over the substrate;

etching the sacrificial material with a first mask to define an edge of the chamber;

etching the sacrificial material with a second mask to form an isolated sacrificial layer having a blade of sacrificial material extending upwards from the substrate.

19. The method of claim 18 , wherein forming the pre-sealing layer over the non-planar sacrificial layer further comprises depositing a dielectric pre-sealing layer over the non-planar sacrificial layer to cover the blade and chamber edge.

20. The method of claim 18 , wherein forming the pre-sealing layer over the non-planar sacrificial layer further comprises depositing a getter layer over the non-planar sacrificial layer to cover the blade.

21. The method of claim 18 , wherein forming the pre-sealing layer over the non-planar sacrificial layer further comprises depositing over the non-planar sacrificial layer a first dielectric layer and a second dielectric layer with a getter layer there between.

22. The method of claim 18 , wherein removing the non-planar sacrificial layer to form the chamber further releases a structural component of a MEMS within the chamber.

23. The method of claim 16 , wherein sealing the pre-sealing layer further comprises:

nonconformally depositing a dielectric to physically occlude the perforation; and

depositing a metal to hermetically seal the perforated pre-sealing layer.

24. The method of claim 16 , further comprising:

depositing a semiconductor over the conductive layer to structurally reinforce the microshell.

25. The method of claim 16 , wherein removing the non-planar sacrificial layer to form the chamber further releases a structural component of a MEMS within the chamber.

26. The method of claim 25 , wherein the released interconnect structure forms an inductor.

27. The method of claim 25 , wherein the released interconnect structure forms a microstrip or coplanar waveguide transmission line.

28. The method of claim 25 , wherein the released interconnect structure is a MEMS resonator.

29. The method of claim 28 , wherein the released interconnect structure is a MEMS resonator that forms a capacitor with the grounded metal-insulator microshell.