IP Library Granted Patent US 8,895,435
Granted Patent B2
US 8,895,435 · App. 13/018,009 · Granted Nov 25, 2014

Polysilicon layer and method of forming the same

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Quick Facts
Patent No.
US 8,895,435
App. No.
13/018,009
Granted
Nov 25, 2014
Kind
B2
Abstract

The method of forming a polysilicon layer is provided. A first polysilicon layer with a first grain size is formed on a substrate. A second polysilicon layer with a second grain size is formed on the first polysilicon layer. The first grain size is smaller than the second grain size. The first polysilicon layer with a smaller grain size can serve as a base for the following deposition, so that the second polysilicon layer formed thereon has a flatter topography, and thus, the surface roughness is reduced and the Rs uniformity within a wafer is improved.

Claims (17)

1. A method of forming a polysilicon layer, comprising:

forming a first polysilicon layer on a substrate, wherein the first polysilicon layer is formed by introducing a silicon-containing gas and an inhibitive gas, and the inhibitive gas is for inhibiting a decomposition rate of the silicon-containing gas; and

forming a second polysilicon layer on the first polysilicon layer, wherein the second polysilicon layer is formed by introducing the silicon-containing gas only,

wherein the silicon-containing gas comprises silane or disilane, and the inhibitive gas comprises hydrogen, and

wherein a flow rate ratio of the silicon-containing gas to the inhibitive gas is from about 1:50 to about 1:60.

2. The method of claim 1 , wherein the first polysilicon layer is amorphous while the second polysilicon layer is crystallized.

3. The method of claim 1 , wherein the first polysilicon layer has a first grain size, the second polysilicon layer has a second grain size, and the first grain size is smaller than the second grain size.

4. The method of claim 1 , wherein a flow rate of the silicon-containing gas is about 50-60 sccm, and a flow rate of the inhibitive gas is about 2,500-3,600 sccm.

5. The method of claim 1 , wherein a flow rate of the silicon-containing gas keeps the same, and a flow rate of the inhibitive gas keeps the same or increases over time.

6. The method of claim 1 , wherein the first polysilicon layer and the second polysilicon layer are formed at the same temperature of about 700-750° C.

7. The method of claim 1 , wherein a temperature of forming the first polysilicon layer is lower than a temperature of forming the second polysilicon layer.

8. The method of claim 7 , wherein the temperature of forming the first polysilicon layer is about 550-650° C., and the temperature of forming the second polysilicon layer is about 700-750° C.

9. The method of claim 1 , wherein a thickness of the first polysilicon layer is smaller than a thickness of the second polysilicon layer.

10. The method of claim 9 , wherein a thickness ratio of the first polysilicon layer to the second polysilicon layer is from about 1:2.5 to about 1:6.

11. The method of claim 10 , wherein the thickness of the first polysilicon layer is about 100-200 Å, and the thickness of the second polysilicon layer is about 500-600 Å.

12. The method of claim 1 , further comprising performing a first ion implantation process after the step of forming the second polysilicon layer to dope the second polysilicon layer.

13. The method of claim 12 , further comprising performing a second ion implantation process before the step of performing the first ion implantation process, so as to form a barrier layer in the second polysilicon layer to prevent dopants from diffusing to the first polysilicon layer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2011
From: LIN, CHIEN-LIANG; WANG, YUN-REN; YEN, YING-WEI; TENG, WEN-YI; YANG, CHAN-LON
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 025749/0088 →