Random access memory devices having word line drivers therein that support variable-frequency clock signals

1. An integrated circuit memory device, comprising:

an array of memory cells electrically coupled to a plurality of word lines;

a word line driver circuit electrically coupled to the plurality of word lines, said word line driver circuit comprising a variable-width pulse generator containing a first delay unit therein, said word line driver circuit configured to drive a selected one of the plurality of word lines with a first word line signal having a leading edge synchronized with a leading edge of a clock signal and a trailing edge synchronized with a trailing edge of the clock signal when a one-half period of the clock signal is greater than a length of delay provided by the first delay unit and further configured to drive the selected one of the plurality of word lines with a second word line signal having a leading edge synchronized with the leading edge of a clock signal and a trailing edge synchronized with an edge of a signal generated by the first delay unit when the one-half period of the clock signal is less than the length of the delay provided by the first delay unit.

2. The memory device of claim 1 , wherein the first delay unit is responsive to the clock signal; and wherein said variable-width pulse generator comprises a logic circuit having a first input terminal responsive to the clock signal and a second input terminal electrically connected to an output of the first delay unit.

3. The memory device of claim 2 , wherein the delay provided by the first delay unit is determined by an odd number of inverters therein.

4. The memory device of claim 2 , wherein said variable-width pulse generator further comprises a totem pole arrangement of a plurality of transistors.

5. The memory device of claim 4 , wherein the logic circuit is an AND gate; and wherein the totem pole arrangement of the plurality of transistors comprises a first PMOS transistor having a gate terminal responsive to the clock signal and a second PMOS transistor having a gate terminal electrically connected to an output of the AND gate.

6. The memory device of claim 5 , wherein the totem pole arrangement of the plurality of transistors further comprises an NMOS transistor having a gate terminal electrically connected to the output of the AND gate.

7. The memory device of claim 6 , wherein the word line driver circuit further comprises a latch having an input terminal electrically connected to an output of the variable-width pulse generator and an output terminal electrically connected to the selected one of the plurality of word lines.

8. The memory device of claim 1 , wherein said variable-width pulse generator comprises:

a logic circuit having a first input terminal responsive to the clock signal and a second input terminal electrically connected to an output of the first delay unit; and

a totem pole arrangement of a plurality transistors, said totem pole arrangement comprising:

a first PMOS pull-up transistor having a gate terminal responsive to the clock signal;

a second PMOS pull-up transistor having a gate terminal electrically connected to an output of the logic circuit; and

an NMOS pull-down transistor having a gate terminal electrically connected to the output of the logic circuit.

9. The memory device of claim 1 , further comprising:

a sense amplifier circuit electrically coupled to said array of memory cells by a plurality of pairs of bit lines; and

a sense amplifier driver configured to drive said sense amplifier with a sense amplifier enable pulse in response to the clock signal.

10. The memory device of claim 9 , wherein said sense amplifier driver comprises a pulse generator containing a second delay unit therein; and wherein a delay provided by the second delay unit sets a duration of the sense amplifier enable pulse.

11. The memory device of claim 10 , wherein a leading edge of the sense amplifier enable pulse is synchronized with a trailing edge of the clock signal.

12. The memory device of claim 11 , further comprising a clock delay circuit configured to generate a delayed clock signal in response to the clock signal; and wherein said sense amplifier driver is responsive to the clock signal and the delayed clock signal.

13. The memory device of claim 12 , wherein said sense amplifier driver further comprises a totem pole arrangement of a plurality of transistors, said totem pole arrangement comprising:

a first PMOS pull-up transistor having a gate terminal responsive to the clock signal;

a second PMOS pull-up transistor having a gate terminal responsive to an inverted version of the delayed clock signal; and

an NMOS pull-down transistor having a gate terminal responsive to the inverted version of the delayed clock signal.

14. An integrated circuit memory device, comprising:

an array of random access memory (RAM) cells electrically coupled to a plurality of word lines;

a word line driver circuit electrically coupled to the plurality of word lines, said word line driver circuit comprising a variable-width pulse generator containing a first delay unit therein, said word line driver circuit configured to drive a selected one of the plurality of word lines with a word line pulse having a minimum duration set by the first delay unit and a maximum duration equivalent to a one-half period of a clock signal.

15. The memory device of claim 14 , wherein said word line driver circuit is configured to operate with clock signals having different frequencies; and wherein an active phase of the word line pulse has a duration equivalent to the minimum duration for all clock signals having periods less than two times a delay provided by the delay unit.

16. A semiconductor memory device comprising:

a memory cell array including a plurality of memory cells;

a bit line pair connected to the memory cell array; and

a word line driver connected to the memory cell array through a word line and driving the word line;

wherein the word line driver adjusts a pulse width of a word line signal provided to the word line according to a frequency of a clock signal, to increase a voltage difference between the bit line pair more than a critical value; and

wherein as the frequency of the clock signal is decreased, the pulse width of the word line signal is increased.

17. The semiconductor memory device of claim 16 , further comprising:

a sense amplifier for sensing a voltage difference of the bit line pair; and

a sense amplifier driver for driving the sense amplifier to sense the voltage difference of the bit line pair after the voltage difference of the bit line pair is increased more than the critical value.

18. The semiconductor memory device of claim 16 , wherein each of the memory cells has a latch structure.

19. A semiconductor memory device comprising:

a memory cell array including a plurality of memory cells;

a bit line pair connected to the memory cell array; and

a word line driver connected to the memory cell array through a word line and driving the word line;

wherein the word line driver adjusts a pulse width of a word line signal provided to the word line according to a frequency of a clock signal, to increase a voltage difference between the bit line pair more than a critical value;

wherein when the frequency of the clock signal is increased more than a reference value, the pulse width of the word line signal has a fixed value.