IP Library › Granted Patent US 8,399,364
Granted Patent B2
US 8,399,364 · App. 13/019,636 · Granted Mar 19, 2013

Methods of fabricating semiconductor devices including multilayer dielectric layers

Inventors: Kil-chul Kim (Seongnam-si, KR); Jong-cheol Lee (Seoul, KR); Ki-vin Im (Seongnam-si, KR); Jae-hyun Yeo (Bucheon-si, KR)
Assignee: Samsung Electronics Co., Ltd.
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Quick Facts
Patent No.
US 8,399,364
App. No.
13/019,636
Granted
Mar 19, 2013
Kind
B2
Abstract

Methods of manufacturing semiconductor devices including multilayer dielectric layers are disclosed. The methods include forming a multilayer dielectric layer including metal atoms and silicon atoms on a semiconductor substrate. The multilayer dielectric layer includes at least two crystalline metal silicate layers having different silicon concentrations. The multilayer dielectric layer may be used, for example, as a dielectric layer for a capacitor, or as a blocking layer for a nonvolatile memory device.

Claims (22)

1. A method of forming a semiconductor device, the method comprising:

forming a multilayer dielectric layer comprising metal atoms and silicon atoms on a semiconductor substrate;

wherein the multilayer dielectric layer comprises at least two crystalline metal silicate layers having different silicon concentrations, which are ratios of silicon atoms with respect to sums of metal atoms and silicon atoms;

wherein forming the multilayer dielectric layer comprises:

forming a first crystalline metal silicate layer having a first silicon concentration in an in-situ crystallized state;

forming a second metal silicate layer having a second silicon concentration that is greater than the first silicon concentration on the first crystalline metal silicate layer; and

forming a second crystalline metal silicate layer by crystallizing the second metal silicate layer using the first crystalline metal silicate as a seed layer.

2. The method of claim 1 , wherein the multilayer dielectric layer has a crystalline structure of a cubic system or an orthorhombic system.

3. The method of claim 1 , wherein the first crystalline metal silicate layer and the second crystalline metal silicate layer comprise zirconium containing silicate.

4. The method of claim 1 , wherein forming the multilayer dielectric layer comprises forming at least two first crystalline metal silicate layers, and forming the second crystalline metal silicate layer between the at least two first crystalline metal silicate layers.

5. The method of claim 1 , wherein a ratio of silicon atoms with respect to a sum of metal atoms and silicon atoms that are included in the multilayer dielectric layer is in the range of about 3% to about 8%.

6. The method of claim 5 , wherein the second silicon concentration is in the range of about 10% to about 20%.

7. A method of forming a semiconductor device, the method comprising:

forming a multilayer dielectric layer comprising metal atoms and silicon atoms on a semiconductor substrate;

wherein the multilayer dielectric layer comprises at least two crystalline metal silicate layers having different silicon concentrations, which are ratios of silicon atoms with respect to sums of metal atoms and silicon atoms;

wherein forming the multilayer dielectric layer comprises:

forming a first crystalline metal silicate layer having a first silicon concentration in an in-situ crystallized state; and

forming a second crystalline metal silicate layer comprises forming the second crystalline metal silicate layer having a second silicon concentration that is greater than the first silicon concentration on the first crystalline metal silicate layer in an in-situ crystallized state using the first crystalline metal silicate layer as a seed.

8. The method of claim 1 , wherein the second metal silicate layer is crystallized at a temperature lower than a temperature that would otherwise be required to crystallize the second metal silicate layer in the absence of the seed layer.

9. The method of claim 1 , wherein the first crystalline metal silicate layer and the second crystalline metal silicate layer comprise hafnium-zirconium silicate.

10. The method of claim 7 , wherein the first crystalline metal silicate layer and the second crystalline metal silicate layer comprise hafnium-zirconium silicate.

11. The method of claim 7 , wherein the multilayer dielectric layer comprises forming at least two first crystalline metal silicate layers, and forming the second crystalline metal silicate layer between the at least two first crystalline metal silicate layers.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 2, 2011
From: KIM, KI-CHUL; LEE, JONG-CHEOL; KIM, KI-VIN; YEO, JAE-HYUN
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 025734/0214 →
Priority Claims (1)
KR 10-2010-0023405 · Mar 16, 2010 · national
Continuity (1)
Related Publication 20110230056A1 · Sep 22, 2011